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| Freescale Semiconductor, Inc. MC68HC908AZ32A Freescale Semiconductor, Inc... Advance Information M68HC08 Microcontrollers MC68HC908AZ32A/D Rev. 0.0, 5/2002 WWW.MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 68HC908AZ32A Advance Information -- Rev 0.0 Freescale Semiconductor, Inc... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. (c) Motorola, Inc., 2002 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Advance Information 4 68HC908AZ32A -- Rev 0.0 MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A List of Paragraphs List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 35 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Section 3. RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . 63 Section 5. EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 95 Section 7. System Integration Module (SIM) . . . . . . . . 113 Section 8. Clock Generator Module (CGM) . . . . . . . . . . 135 Section 9. Configuration Register (CONFIG-1). . . . . . . 163 Section 10. Configuration Register (CONFIG-2). . . . . . 167 Section 11. Break Module. . . . . . . . . . . . . . . . . . . . . . . . 169 Section 12. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 175 Section 13. Computer Operating Properly (COP) . . . . 187 Section 14. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . . 193 Section 15. External Interrupt Module (IRQ1) . . . . . . . . 199 68HC908AZ32A -- Rev 0.0 MOTOROLA List of Paragraphs For More Information On This Product, Go to: www.freescale.com Advance Information 5 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. List of Paragraphs Section 16. Serial Communications Interface (SCI) . . . 207 Section 17. Serial Peripheral Interface (SPI). . . . . . . . . 247 Section 18. Timer Interface Module A (TIMA) . . . . . . . . 279 Section 19. Timer Interface Module B (TIMB) . . . . . . . . 311 Section 20. Programmable Interrupt Timer (PIT) . . . . . 335 Section 21. Analog-To-Digital Converter (ADC-15) . . . 345 Section 22. Keyboard Module (KBD) . . . . . . . . . . . . . . . 357 Section 23. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Section 24. MSCAN Controller (MSCAN08) . . . . . . . . . 391 Section 25. Electrical Specification . . . . . . . . . . . . . . . . 443 Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Freescale Semiconductor, Inc... Advance Information 6 68HC908AZ32A -- Rev 0.0 List of Paragraphs For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Table of Contents List of Paragraphs Table of Contents List of Figures List of Tables Section 1. General Description 1.1 1.2 1.3 1.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Freescale Semiconductor, Inc... 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 1.5.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . . 40 1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 41 1.5.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.5.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.5.5 Analog Power Supply Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . 41 1.5.6 Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.5.7 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . 41 1.5.8 ADC Analog Power Supply Pin (VDDAREF) . . . . . . . . . . . . 42 1.5.9 ADC Analog Ground Pin (AVSS/VREFL). . . . . . . . . . . . . . . 42 1.5.10 ADC Reference High Voltage Pin (VREFH). . . . . . . . . . . . . 42 1.5.11 Port A Input/Output (I/O) Pins (PTA7-PTA0) . . . . . . . . . . . . 42 1.5.12 Port B I/O Pins (PTB7/ATD7-PTB0/ATD0) . . . . . . . . . . . . .42 1.5.13 Port C I/O Pins (PTC5-PTC0) . . . . . . . . . . . . . . . . . . . . . . . 42 1.5.14 Port D I/O Pins (PTD7-PTD0/ATD8) . . . . . . . . . . . . . . . . . . 43 68HC908AZ32A -- Rev 0.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com Advance Information 7 Freescale Semiconductor, Inc. Table of Contents 1.5.15 1.5.16 1.5.17 1.5.18 1.5.19 1.5.20 Port E I/O Pins (PTE7/SPSCK-PTE0/TxD) . . . . . . . . . . . . . 43 Port F I/O Pins (PTF6-PTF0/TACH2) . . . . . . . . . . . . . . . . . 43 Port G I/O Pins (PTG2/KBD2-PTG0/KBD0) . . . . . . . . . . . . 43 Port H I/O Pins (PTH1/KBD4-PTH0/KBD3). . . . . . . . . . . . . 44 CAN Transmit Pin (CANTx) . . . . . . . . . . . . . . . . . . . . . . . . . 44 CAN Receive Pin (CANRx) . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.6 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1.6.1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Freescale Semiconductor, Inc... Section 2. Memory Map 2.1 2.2 2.3 2.4 2.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Additional Status and Control Registers . . . . . . . . . . . . . . . . . . 57 Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . . . . 59 Section 3. RAM 3.1 3.2 3.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Section 4. FLASH Memory 4.1 4.2 4.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4 FLASH Control and Block Protect Registers . . . . . . . . . . . . . . 64 4.4.1 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.2 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . .66 4.5 4.6 Advance Information 8 Table of Contents For More Information On This Product, Go to: www.freescale.com FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 69 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Table of Contents 4.7 4.8 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 70 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4.9.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.9.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Section 5. EEPROM 5.1 5.2 5.3 5.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 EEPROM Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Freescale Semiconductor, Inc... 5.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.5.1 EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.5.2 EEPROM Timebase Requirements . . . . . . . . . . . . . . . . . . . 78 5.5.3 EEPROM Program/Erase Protection . . . . . . . . . . . . . . . . . . 79 5.5.4 EEPROM Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.5.5 EEPROM Programming and Erasing . . . . . . . . . . . . . . . . . . 80 5.6 EEPROM Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 84 5.6.1 EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.6.2 EEPROM Array Configuration Register . . . . . . . . . . . . . . . .87 5.6.3 EEPROM Nonvolatile Register. . . . . . . . . . . . . . . . . . . . . . .89 5.6.4 EEPROM Timebase Divider Register . . . . . . . . . . . . . . . . . 89 5.6.5 EEPROM Timebase Divider Non-Volatile Register . . . . . . . 91 5.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 5.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Section 6. Central Processor Unit (CPU) 6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 68HC908AZ32A -- Rev 0.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com Advance Information 9 Freescale Semiconductor, Inc. Table of Contents 6.4 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.4.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 6.4.2 Index register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.4.3 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.4.4 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.4.5 Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . .99 6.5 Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Freescale Semiconductor, Inc... 6.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 6.6.1 WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.6.2 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.7 6.8 6.9 CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Section 7. System Integration Module (SIM) 7.1 7.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 116 7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . 117 7.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 117 7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 118 7.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 119 7.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . 121 7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 122 7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 122 7.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 123 7.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .123 Advance Information 10 Table of Contents For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Table of Contents 7.6 Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 7.6.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 7.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 128 7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.8.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 133 7.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 134 Freescale Semiconductor, Inc... Section 8. Clock Generator Module (CGM) 8.1 8.2 8.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .139 8.4.2.1 Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.4.2.2 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . 141 8.4.2.3 Manual and Automatic PLL Bandwidth Modes . . . . . . . 141 8.4.2.4 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . .143 8.4.2.5 Special Programming Exceptions . . . . . . . . . . . . . . . . . 145 8.4.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . 145 8.4.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . 146 8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . 147 8.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . 147 8.5.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . 147 8.5.4 Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.5.5 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . 148 8.5.6 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . 148 68HC908AZ32A -- Rev 0.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com Advance Information 11 Freescale Semiconductor, Inc. Table of Contents 8.5.7 8.5.8 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . . 148 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 148 8.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 8.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 8.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . 151 8.6.3 PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . . 153 8.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Freescale Semiconductor, Inc... 8.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 8.9 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 156 8.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .156 8.10.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . . 156 8.10.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . 158 8.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 159 8.10.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . 159 Section 9. Configuration Register (CONFIG-1) 9.1 9.2 9.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Section 10. Configuration Register (CONFIG-2) 10.1 10.2 10.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Section 11. Break Module 11.1 11.2 11.3 Advance Information 12 Table of Contents For More Information On This Product, Go to: www.freescale.com Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Table of Contents 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .171 11.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 171 11.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 172 11.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 172 11.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 11.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 11.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . 173 11.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .174 Freescale Semiconductor, Inc... Section 12. Monitor ROM (MON) 12.1 12.2 12.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 12.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 12.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 12.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 12.4.4 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 12.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 12.4.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 12.4.7 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Section 13. Computer Operating Properly (COP) 13.1 13.2 13.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 68HC908AZ32A -- Rev 0.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com Advance Information 13 Freescale Semiconductor, Inc. Table of Contents 13.4.4 13.4.5 13.4.6 13.4.7 13.4.8 13.5 13.6 13.7 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 COPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 COPRS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Freescale Semiconductor, Inc... 13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 13.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.9 COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 192 Section 14. Low Voltage Inhibit (LVI) 14.1 14.2 14.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.4.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.4.3 False Reset Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.5 14.6 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Section 15. External Interrupt Module (IRQ1) 15.1 15.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Advance Information 14 Table of Contents For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Table of Contents 15.3 15.4 15.5 15.6 15.7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .204 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 204 Section 16. Serial Communications Interface (SCI) 16.1 16.2 16.3 16.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Freescale Semiconductor, Inc... 16.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 16.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.5.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.5.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.5.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 16.5.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . . 217 16.5.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 217 16.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 16.5.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 16.5.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 16.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 16.5.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 16.5.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 16.5.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16.5.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 16.5.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 68HC908AZ32A -- Rev 0.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com Advance Information 15 Freescale Semiconductor, Inc. Table of Contents 16.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 228 16.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 16.8.1 PTE0/SCTxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . 228 16.8.2 PTE1/SCRxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . 229 16.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 16.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 16.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 16.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 16.9.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 16.9.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 16.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Freescale Semiconductor, Inc... Section 17. Serial Peripheral Interface (SPI) 17.1 17.2 17.3 17.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Pin Name and Register Name Conventions . . . . . . . . . . . . . . 249 17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 17.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 17.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 17.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 17.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . 254 17.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . 255 17.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . 256 17.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . 257 17.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.7.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 17.8 17.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 264 17.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Advance Information 16 Table of Contents For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Table of Contents 17.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 17.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 17.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 17.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .267 17.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 17.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . . 268 17.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . . 269 17.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 17.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 17.13.5 VSS (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 17.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 17.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 17.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . 274 17.14.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Freescale Semiconductor, Inc... Section 18. Timer Interface Module A (TIMA) 18.1 18.2 18.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.4.1 TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 18.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 285 18.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 286 18.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 287 18.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 288 18.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 289 18.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 18.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 68HC908AZ32A -- Rev 0.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com Advance Information 17 Freescale Semiconductor, Inc. Table of Contents 18.7 TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 293 18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 18.8.1 TIMA Clock Pin (PTD6/ATD14/TACLK) . . . . . . . . . . . . . . .294 18.8.2 TIMA Channel I/O Pins (PTF3/TCH5-PTF0/TCH2 and PTE3/TCH1-PTE2/TCH0) . . . . . . . . . . . . . . . . . . . . . . . . . 294 18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 18.9.1 TIMA Status and Control Register . . . . . . . . . . . . . . . . . . .295 18.9.2 TIMA Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 297 18.9.3 TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 298 18.9.4 TIMA Channel Status and Control Registers . . . . . . . . . . . 299 18.9.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .306 Freescale Semiconductor, Inc... Section 19. Timer Interface Module B (TIMB) 19.1 19.2 19.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 19.4.1 TIMB Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . 314 19.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 19.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 19.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 316 19.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 317 19.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 318 19.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 319 19.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 320 19.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 19.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 19.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 19.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 19.7 TIMB During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 323 19.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 19.8.1 TIMB Clock Pin (PTD4/ATD12) . . . . . . . . . . . . . . . . . . . . . 323 Advance Information 18 Table of Contents For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Table of Contents 19.8.2 TIMB Channel I/O Pins (PTF5/TBCH1-PTF4). . . . . . . . . . 324 19.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 19.9.1 TIMB Status and Control Register . . . . . . . . . . . . . . . . . . .324 19.9.2 TIMB Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 327 19.9.3 TIMB Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 328 19.9.4 TIMB Channel Status and Control Registers . . . . . . . . . . . 328 19.9.5 TIMB Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .333 Section 20. Programmable Interrupt Timer (PIT) 20.1 20.2 20.3 20.4 20.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 PIT Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 Freescale Semiconductor, Inc... 20.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 20.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 20.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 20.7 PIT During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .338 20.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 20.8.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 339 20.8.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 20.8.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 343 Section 21. Analog-To-Digital Converter (ADC-15) 21.1 21.2 21.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 21.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 21.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 21.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 68HC908AZ32A -- Rev 0.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com Advance Information 19 Freescale Semiconductor, Inc. Table of Contents 21.4.4 21.4.5 21.5 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 21.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 21.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 21.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 21.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 21.7.1 ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 21.7.2 ADC Analog Ground Pin (VSSA)/ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 21.7.3 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 350 21.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 21.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 351 21.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 21.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 354 Freescale Semiconductor, Inc... Section 22. Keyboard Module (KBD) 22.1 22.2 22.3 22.4 22.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 22.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 22.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 22.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .362 22.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 22.8.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 363 22.8.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 364 Section 23. I/O Ports Advance Information 20 Table of Contents For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Table of Contents 23.1 23.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 23.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 23.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 23.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . 367 23.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 23.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 23.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . 370 23.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 23.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 23.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . 373 23.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375 23.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 376 23.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 23.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 23.7.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . 380 23.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 23.8.1 Port F Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 23.8.2 Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . . . 383 23.9 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385 23.9.1 Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 23.9.2 Data Direction Register G . . . . . . . . . . . . . . . . . . . . . . . . . 386 23.10 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 23.10.1 Port H Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 23.10.2 Data Direction Register H. . . . . . . . . . . . . . . . . . . . . . . . . . 389 Freescale Semiconductor, Inc... Section 24. MSCAN Controller (MSCAN08) 24.1 24.2 24.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 68HC908AZ32A -- Rev 0.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com Advance Information 21 Freescale Semiconductor, Inc. Table of Contents 24.4 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 24.5 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 24.5.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 24.5.2 Receive Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 24.5.3 Transmit Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 24.6 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 Freescale Semiconductor, Inc... 24.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 24.7.1 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 24.7.2 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 24.8 Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . . 406 24.9 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406 24.9.1 MSCAN08 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 24.9.2 MSCAN08 Soft Reset Mode. . . . . . . . . . . . . . . . . . . . . . . . 409 24.9.3 MSCAN08 Power Down Mode . . . . . . . . . . . . . . . . . . . . . .409 24.9.4 CPU Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410 24.9.5 Programmable Wakeup Function. . . . . . . . . . . . . . . . . . . . 410 24.10 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 24.11 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 24.12 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 24.13 Programmer's Model of Message Storage . . . . . . . . . . . . . . .416 24.13.1 Message Buffer Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 24.13.2 Identifier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 24.13.3 Data Length Register (DLR). . . . . . . . . . . . . . . . . . . . . . . . 419 24.13.4 Data Segment Registers (DSRn) . . . . . . . . . . . . . . . . . . . . 420 24.13.5 Transmit Buffer Priority Registers . . . . . . . . . . . . . . . . . . .421 24.14 Programmer's Model of Control Registers . . . . . . . . . . . . . . . 421 24.14.1 MSCAN08 Module Control Register 0 . . . . . . . . . . . . . . . . 424 24.14.2 MSCAN08 Module Control Register 1 . . . . . . . . . . . . . . . . 426 24.14.3 MSCAN08 Bus Timing Register 0 . . . . . . . . . . . . . . . . . . .427 24.14.4 MSCAN08 Bus Timing Register 1 . . . . . . . . . . . . . . . . . . .428 24.14.5 MSCAN08 Receiver Flag Register (CRFLG) . . . . . . . . . . . 430 24.14.6 MSCAN08 Receiver Interrupt Enable Register . . . . . . . . . 433 24.14.7 MSCAN08 Transmitter Flag Register. . . . . . . . . . . . . . . . . 434 Advance Information 22 Table of Contents For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Table of Contents 24.14.8 24.14.9 24.14.10 24.14.11 24.14.12 24.14.13 MSCAN08 Transmitter Control Register . . . . . . . . . . . . . . 436 MSCAN08 Identifier Acceptance Control Register. . . . . . . 437 MSCAN08 Receive Error Counter . . . . . . . . . . . . . . . . . . .438 MSCAN08 Transmit Error Counter. . . . . . . . . . . . . . . . . . . 439 MSCAN08 Identifier Acceptance Registers . . . . . . . . . . . .439 MSCAN08 Identifier Mask Registers (CIDMR0-3) . . . . . . . 441 Section 25. Electrical Specification 25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 Freescale Semiconductor, Inc... 25.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 25.2.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 25.2.2 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . 445 25.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 25.2.4 5.0 Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . 446 25.2.5 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 25.2.6 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 25.2.7 5.0 Vdc 0.5 V Serial Peripheral Interface (SPI) Timing . . 449 25.2.8 CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . 452 25.2.9 CGM Component Information . . . . . . . . . . . . . . . . . . . . . . 452 25.2.10 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . 453 25.2.11 Timer Module Characteristics. . . . . . . . . . . . . . . . . . . . . . . 454 25.2.12 RAM Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . 454 25.2.13 EEPROM Memory Characteristics . . . . . . . . . . . . . . . . . . . 454 25.2.14 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . 455 25.3 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 25.3.1 64-Pin Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . . . . 456 Glossary 68HC908AZ32A -- Rev 0.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com Advance Information 23 Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... Advance Information 24 Table of Contents For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A List of Figures Figure 1-1 1-2 1-3 2-1 2-2 2-3 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 6-1 6-2 6-3 6-4 6-5 7-1 7-2 7-3 7-4 7-5 Title Page MCU Block Diagram for the MC68HC908AZ32A . . . . . . . . . . . 38 MC68HC908AZ32A 64 QFP Pin Assignments. . . . . . . . . . . . . 39 Power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 I/O Data, Status and Control Registers . . . . . . . . . . . . . . . . . . 53 Additional Status and Control Registers . . . . . . . . . . . . . . . . . . 57 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . . 65 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . . 66 FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . . 66 FLASH Programming Algorithm Flowchart. . . . . . . . . . . . . . . .73 EEPROM Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 77 EEPROM Control Register (EECR) . . . . . . . . . . . . . . . . . . . . . 85 EEPROM Array Configuration Register (EEACR) . . . . . . . . . . 87 EEPROM Nonvolatile Register (EENVR) . . . . . . . . . . . . . . . . . 89 EEDIV Divider High Register (EEDIVH) . . . . . . . . . . . . . . . . . . 90 EEDIV Divider Low Register (EEDIVL). . . . . . . . . . . . . . . . . . . 90 EEPROM Divider Non-Volatile Register High (EEDIVHNVR)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 EEPROM Divider Non-Volatile Register Low (EEDIVLNVR) . . 92 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Index register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Program counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 99 SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 115 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information List of Figures For More Information On This Product, Go to: www.freescale.com 25 Freescale Semiconductor, Inc. List of Figures 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 8-1 8-2 8-3 8-4 8-5 8-6 9-1 10-1 11-1 11-2 11-3 11-4 12-1 12-2 12-3 12-4 12-5 12-6 13-1 13-2 14-1 14-2 14-3 15-1 Advance Information 26 List of Figures For More Information On This Product, Go to: www.freescale.com Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 127 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 129 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . 130 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . 131 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 132 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . 133 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 134 CGM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . .147 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 149 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . . 151 PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . . . 153 Configuration Register (CONFIG-1) . . . . . . . . . . . . . . . . . . . . 164 Configuration Register (CONFIG-2) . . . . . . . . . . . . . . . . . . . . 167 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 170 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Break Status and Control Register (BSCR) . . . . . . . . . . . . . . 173 Break Address Registers (BRKH and BRKL) . . . . . . . . . . . . . 174 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 186 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . .191 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 LVI Status Register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 197 IRQ Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. List of Figures 15-2 15-3 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 16-18 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 18-1 18-2 18-3 18-4 18-5 68HC908AZ32A -- Rev 0.0 MOTOROLA IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 204 SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 210 SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 SCI Transmitter I/O Register Summary . . . . . . . . . . . . . . . . . 215 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . 218 SCI I/O Receiver Register Summary . . . . . . . . . . . . . . . . . . .219 Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . . 230 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . . 233 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . . 236 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . . 238 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . . 242 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . . 243 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . . 252 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 255 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . 256 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . 258 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . . 260 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 261 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 264 SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . . 265 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 272 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . .275 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 TIMA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 TIMA I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 282 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 288 TIMA Status and Control Register (TASC) . . . . . . . . . . . . . . .295 TIMA Counter Registers (TACNTH and TACNTL) . . . . . . . . . 298 Advance Information Freescale Semiconductor, Inc... List of Figures For More Information On This Product, Go to: www.freescale.com 27 Freescale Semiconductor, Inc. List of Figures 18-6 18-7 18-7 18-8 18-9 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 20-1 20-2 20-3 20-4 20-5 21-1 21-2 21-3 21-4 22-1 22-2 22-3 22-4 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 Advance Information 28 List of Figures For More Information On This Product, Go to: www.freescale.com TIMA Counter Modulo Registers (TAMODH and TAMODL) . 299 TIMA Channel Status and Control Registers (TASC0-TASC5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 TIMA Channel Status and Control Registers (TASC0-TASC5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 TIMA Channel Registers (TACH0H/L-TACH5H/L) . . . . . . . . 307 TIMB Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 TIMB I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 313 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 318 TIMB Status and Control Register (TBSC) . . . . . . . . . . . . . . .325 TIMB Counter Registers (TBCNTH and TBCNTL) . . . . . . . . . 327 TIMB Counter Modulo Registers (TBMODH and TBMODL) . 328 TIMB Channel Status and Control Registers (TBSC0-TBSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 TIMB Channel Registers (TBCH0H/L-TBCH1H/L) . . . . . . . . 334 PIT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 PIT I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 PIT Status and Control Register (PSC) . . . . . . . . . . . . . . . . . 339 PIT Counter Registers (PCNTH-PCNTL). . . . . . . . . . . . . . . . 342 PIT Counter Modulo Registers (PMODH-PMODL) . . . . . . . . 343 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 351 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .354 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . . 359 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 Keyboard Status and Control Register (KBSCR) . . . . . . . . . . 363 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . . 364 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .367 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 367 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .369 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 370 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .372 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. List of Figures Freescale Semiconductor, Inc... 23-9 23-10 23-11 23-12 23-13 23-14 23-15 23-16 23-17 23-18 23-19 23-20 23-21 23-22 23-23 23-24 23-25 24-1 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 24-10 24-11 24-12 24-13 24-14 24-15 24-16 24-17 24-18 24-19 24-20 68HC908AZ32A -- Rev 0.0 MOTOROLA Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 373 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .375 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 376 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .378 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 380 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . . 382 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . . 383 Port F I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 Port G Data Register (PTG) . . . . . . . . . . . . . . . . . . . . . . . . . .385 Data Direction Register G (DDRG). . . . . . . . . . . . . . . . . . . . . 386 Port G I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . .388 Data Direction Register H (DDRH) . . . . . . . . . . . . . . . . . . . . . 389 Port H I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 User Model for Message Buffer Organization. . . . . . . . . . . . . 398 Single 32-Bit Maskable Identifier Acceptance Filter . . . . . . . .401 Dual 16-Bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . 402 Quadruple 8-Bit Maskable Acceptance Filters . . . . . . . . . . . .403 Sleep Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . 408 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Segments within the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . . 413 MSCAN08 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 Message Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . . 416 Receive/Transmit Message Buffer Extended Identifier (IDRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 Standard Identifier Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .418 Transmit Buffer Priority Register (TBPR) . . . . . . . . . . . . . . . . 421 MSCAN08 Control Register Structure . . . . . . . . . . . . . . . . . . 422 Module Control Register 0 (CMCR0) . . . . . . . . . . . . . . . . . . .424 Module Control Register (CMCR1). . . . . . . . . . . . . . . . . . . . . 426 Bus Timing Register 0 (CBTR0) . . . . . . . . . . . . . . . . . . . . . . . 427 Bus Timing Register 1 (CBTR1) . . . . . . . . . . . . . . . . . . . . . . . 428 Receiver Flag Register (CRFLG) . . . . . . . . . . . . . . . . . . . . . . 430 Receiver Interrupt Enable Register (CRIER) . . . . . . . . . . . . . 433 Advance Information List of Figures For More Information On This Product, Go to: www.freescale.com 29 Freescale Semiconductor, Inc. List of Figures 24-21 24-22 24-23 24-24 24-25 24-26 24-27 25-1 25-2 Transmitter Flag Register (CTFLG) . . . . . . . . . . . . . . . . . . . . 434 Transmitter Control Register (CTCR) . . . . . . . . . . . . . . . . . . . 436 Identifier Acceptance Control Register (CIDAC). . . . . . . . . . . 437 Receiver Error Counter (CRXERR) . . . . . . . . . . . . . . . . . . . . 438 Transmit Error Counter (CTXERR). . . . . . . . . . . . . . . . . . . . . 439 Identifier Acceptance Registers (CIDAR0-CIDAR3) . . . . . . . 440 Identifier Mask Registers (CIDMR0-CIDMR3) . . . . . . . . . . . . 441 SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .450 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 Freescale Semiconductor, Inc... Advance Information 30 List of Figures For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A List of Tables Table 1-1 1-3 1-2 1-4 2-1 5-1 5-2 5-3 5-4 6-1 6-2 7-1 7-2 7-3 8-1 8-2 8-3 11-1 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 14-1 15-1 Title Page External Pins Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Clock Signal Naming Conventions . . . . . . . . . . . . . . . . . . . . . . 47 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 EEPROM Array Address Blocks. . . . . . . . . . . . . . . . . . . . . . . . 80 Example Selective Bit Programming Description . . . . . . . . . . . 81 EEPROM Program/Erase Mode Select . . . . . . . . . . . . . . . . . . 85 EEPROM Block Protect and Security Summary. . . . . . . . . . . . 88 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . . 116 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . . 139 Variable Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 VCO Frequency Multiplier (N) Selection. . . . . . . . . . . . . . . . . 154 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . . 171 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 181 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 182 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 182 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 183 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . .183 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 184 68HC908AZ32A Monitor Baud Rate Selection . . . . . . . . . . . 184 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information List of Tables For More Information On This Product, Go to: www.freescale.com 31 Freescale Semiconductor, Inc. List of Tables 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 17-1 17-2 17-3 17-4 17-5 17-6 18-1 18-2 19-1 19-2 20-1 20-2 21-1 21-2 22-1 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 24-1 24-2 24-3 24-4 Advance Information 32 List of Tables For More Information On This Product, Go to: www.freescale.com Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 SCI I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . 211 SCI Transmitter I/O Address Summary . . . . . . . . . . . . . . . . . 215 SCI Receiver I/O Address Summary . . . . . . . . . . . . . . . . . . .219 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .232 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . 245 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 I/O Register Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . 277 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . .305 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . .332 PIT I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . 337 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . . 359 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Port F Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 Port G Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Port H Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 MSCAN08 Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . 405 MSCAN08 vs CPU operating modes . . . . . . . . . . . . . . . . . . .407 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 Time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. List of Tables 24-5 24-6 24-7 24-8 24-9 24-10 24-11 CAN Standard Compliant Bit Time Segment Settings . . . . . . 414 Data Length Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 Synchronization Jump Width . . . . . . . . . . . . . . . . . . . . . . . . . 427 Baud Rate Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Time Segment Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Identifier Acceptance Mode Settings . . . . . . . . . . . . . . . . . . .437 Identifier Acceptance Hit Indication . . . . . . . . . . . . . . . . . . . . 438 Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA List of Tables For More Information On This Product, Go to: www.freescale.com Advance Information 33 Freescale Semiconductor, Inc. List of Tables Freescale Semiconductor, Inc... Advance Information 34 List of Tables For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 1. General Description 1.1 Contents 1.2 1.3 1.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Freescale Semiconductor, Inc... 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 1.5.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . . 40 1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 41 1.5.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.5.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.5.5 Analog Power Supply Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . 41 1.5.6 Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.5.7 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . 41 1.5.8 ADC Analog Power Supply Pin (VDDAREF) . . . . . . . . . . . . 42 1.5.9 ADC Analog Ground Pin (AVSS/VREFL). . . . . . . . . . . . . . . 42 1.5.10 ADC Reference High Voltage Pin (VREFH). . . . . . . . . . . . . 42 1.5.11 Port A Input/Output (I/O) Pins (PTA7-PTA0) . . . . . . . . . . . . 42 1.5.12 Port B I/O Pins (PTB7/ATD7-PTB0/ATD0) . . . . . . . . . . . . .42 1.5.13 Port C I/O Pins (PTC5-PTC0) . . . . . . . . . . . . . . . . . . . . . . . 42 1.5.14 Port D I/O Pins (PTD7-PTD0/ATD8) . . . . . . . . . . . . . . . . . . 43 1.5.15 Port E I/O Pins (PTE7/SPSCK-PTE0/TxD) . . . . . . . . . . . . . 43 1.5.16 Port F I/O Pins (PTF6-PTF0/TACH2) . . . . . . . . . . . . . . . . . 43 1.5.17 Port G I/O Pins (PTG2/KBD2-PTG0/KBD0) . . . . . . . . . . . . 43 1.5.18 Port H I/O Pins (PTH1/KBD4-PTH0/KBD3). . . . . . . . . . . . . 44 1.5.19 CAN Transmit Pin (CANTx) . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.5.20 CAN Receive Pin (CANRx) . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.6 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1.6.1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 68HC908AZ32A -- Rev 0.0 MOTOROLA General Description For More Information On This Product, Go to: www.freescale.com Advance Information 35 Freescale Semiconductor, Inc. General Description 1.2 Introduction The 68HC908AZ32A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 1.3 Features Features of the 68HC908AZ32A include: * * * * * * * * * * * * * * * High-Performance M68HC08 Architecture Fully Upward-Compatible Object Code with M6805, M146805, and M68HC05 Families 8.4 MHz Internal Bus Frequency 32,256 bytes of FLASH Electrically Erasable Read-Only Memory (FLASH) FLASH Data Security 512 bytes of On-Chip Electrically Erasable Programmable ReadOnly Memory with Security Option (EEPROM) 1K byte of On-Chip RAM Clock Generator Module (CGM) Serial Peripheral Interface Module (SPI) Serial Communications Interface Module (SCI) 8-Bit, 15-Channel Analog-to-Digital Converter (ADC-15) 16-Bit, 6-Channel Timer Interface Module (TIMA-6) 16-Bit, 2-Channel Timer Interface Module (TIMB) Programmable Interrupt Timer (PIT) System Protection Features - Computer Operating Properly (COP) with Optional Reset - Low-Voltage Detection with Optional Reset Advance Information 36 General Description For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. General Description MCU Block Diagram - Illegal Opcode Detection with Optional Reset - Illegal Address Detection with Optional Reset * * * * Low-Power Design (Fully Static with Stop and Wait Modes) Master Reset Pin and Power-On Reset 5-Bit Keyboard Interrupt Module MSCAN Controller (Motorola Scalable CAN) implements CAN 2.0b Protocol as Defined in BOSCH Specification September 1991 Freescale Semiconductor, Inc... Features of the CPU08 include: * * * * * * * * * * Enhanced HC05 Programming Model Extensive Loop Control Functions 16 Addressing Modes (Eight More Than the HC05) 16-Bit Index Register and Stack Pointer Memory-to-Memory Data Transfers Fast 8 x 8 Multiply Instruction Fast 16/8 Divide Instruction Binary-Coded Decimal (BCD) Instructions Optimization for Controller Applications C Language Support 1.4 MCU Block Diagram Figure 1-1 shows the structure of the 68HC908AZ32A 68HC908AZ32A -- Rev 0.0 MOTOROLA General Description For More Information On This Product, Go to: www.freescale.com Advance Information 37 Freescale Semiconductor, Inc... CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) VREFH DDRA PTA DDRC PTC DDRD PTD OSC1 OSC2 CGMXFC SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MODULE CLOCK GENERATOR MODULE DDRE TIMER B INTERFACE MODULE PTE DDRF PTF Freescale Semiconductor, Inc. VSS VDD VDDA VSSA POWER DDRH DDRG AVSS/VREFL VDDAREF MSCAN MODULE PTH General Description For More Information On This Product, Go to: www.freescale.com COMPUTER OPERATING PROPERLY MODULE TIMER A 6 CHANNEL INTERFACE MODULE POWER-ON RESET MODULE PTG Advance Information PTA7-PTA0 BREAK MODULE CONTROL AND STATUS REGISTERS -- 62 BYTES PTC5-PTC3 PTC2/MCLK PTC1-PTC0 General Description USER FLASH -- 32,256 BYTES LOW-VOLTAGE INHIBIT MODULE USER RAM --1024 BYTES DDRB PTB 38 ANALOG-TO-DIGITAL MODULE PTB7/ATD7-PTB0/ATD0 PTD7 PTD6/ATD14/TACLK PTD5/ATD13 PTD4/ATD12/TBCLK PTD3/ATD11-PTD0/ATD8 M68HC08 CPU USER EEPROM -- 512 BYTES MONITOR ROM -- 320 BYTES USER FLASH VECTOR SPACE -- 52 BYTES PTE7/SPSCK PTE6/MOSI PTE5/MISO PTE4/SS PTE3/TACH1 PTE2/TACH0 PTE1/RxD PTE0/TxD PTF6 PTF5/TBCH1-PTF4/TBCH0 PTF3/TACH5-PTF0/TACH2 RST SYSTEM INTEGRATION MODULE IRQ IRQ MODULE KEYBOARD INTERRUPT MODULE PTG2/KBD2-PTG0/KBD0 PROGRAMMABLE INTERRUPT TIMER MODULE PTH1/KBD4-PTH0/KBD3 CANRx CANTx 68HC908AZ32A -- Rev 0.0 MOTOROLA Figure 1-1. MCU Block Diagram for the MC68HC908AZ32A Freescale Semiconductor, Inc. General Description Pin Assignments 1.5 Pin Assignments Figure 1-2 shows the 68HC908AZ32A pin assignments. PTD6/ATD14/TACLK PTD4/ATD12/TBCLK 50 PTD5/ATD13 PTC2/MCLK Freescale Semiconductor, Inc... 64 63 62 61 60 59 58 57 56 55 54 53 52 PTC4 IRQ RST PTF0/TACH2 PTF1/TACH3 PTF2/TACH4 PTF3/TACH5 PTF4/TBCH0 CANRx CANTx PTF5/TBCH1 PTF6 PTE0/TxD PTE1/RxD PTE2/TACH0 PTE3/TACH1 51 49 PTH1/KBD4 CGMXFC VREFH OSC1 OSC2 PTC5 PTC3 PTC1 PTC0 PTD7 VDDA VSSA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 PTH0/KBD3 PTD3/ATD11 PTD2/ATD10 AVSS /VREFL VDDAREF PTD1/ATD9 PTD0/ATD8 PTB7/ATD7 PTB6/ATD6 PTB5/ATD5 PTB4/ATD4 PTB3/ATD3 PTB2/ATD2 PTB1/ATD1 PTB0/ATD0 18 19 20 21 22 23 24 25 26 27 28 29 30 PTE4/SS 17 31 16 33 PTA6 32 PTA7 PTE5/MISO PTE6/MOSI VSS PTE7/SPSCK VDD PTA0 PTA1 PTA2 PTA3 PTA4 PTG0/KBD0 PTG1/KBD1 Figure 1-2. MC68HC908AZ32A 64 QFP Pin Assignments 68HC908AZ32A -- Rev 0.0 MOTOROLA General Description For More Information On This Product, Go to: www.freescale.com PTG2/KBD2 PTA5 Advance Information 39 Freescale Semiconductor, Inc. General Description NOTE: The following pin descriptions are just a quick reference. For a more detailed representation, see Section 23. I/O Ports. 1.5.1 Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as shown in Figure 1-3. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. Figure 1-3. Power supply bypassing Freescale Semiconductor, Inc... MCU VDD VSS C1 0.1 F + C2 VDD NOTE: Component values shown represent typical applications. VSS is also the ground for the port output buffers and the ground return for the serial clock in the Serial Peripheral Interface module (SPI). See Section 17. Serial Peripheral Interface (SPI). NOTE: VSS must be grounded for proper MCU operation. Advance Information 40 General Description For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. General Description Pin Assignments 1.5.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Section 8. Clock Generator Module (CGM). 1.5.3 External Reset Pin (RST) A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. See Section 7. System Integration Module (SIM) for more information. Freescale Semiconductor, Inc... 1.5.4 External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. See Section 15. External Interrupt Module (IRQ1). 1.5.5 Analog Power Supply Pin (VDDA) VDDA is the power supply pin for the analog portion of the Clock Generator Module (CGM). See Section 8. Clock Generator Module (CGM). 1.5.6 Analog Ground Pin (VSSA) VSSA is the ground connection for the analog portion of the Clock Generator Module (CGM). See Section 8. Clock Generator Module (CGM). 1.5.7 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the Clock Generator Module (CGM). See Section 8. Clock Generator Module (CGM). 68HC908AZ32A -- Rev 0.0 MOTOROLA General Description For More Information On This Product, Go to: www.freescale.com Advance Information 41 Freescale Semiconductor, Inc. General Description 1.5.8 ADC Analog Power Supply Pin (VDDAREF) VDDAREF is the power supply pin for the analog portion of the Analog-toDigital Converter (ADC). See Section 21. Analog-To-Digital Converter (ADC-15). 1.5.9 ADC Analog Ground Pin (AVSS/VREFL) The AVSS/VREFL pin provides both the analog ground connection and the reference low voltage for the Analog-to-Digital Converter (ADC). See Section 21. Analog-To-Digital Converter (ADC-15). Freescale Semiconductor, Inc... 1.5.10 ADC Reference High Voltage Pin (VREFH) VREFH provides the reference high voltage for the Analog-to-Digital Converter (ADC). See Section 21. Analog-To-Digital Converter (ADC-15). 1.5.11 Port A Input/Output (I/O) Pins (PTA7-PTA0) PTA7-PTA0 are general-purpose bidirectional I/O port pins. See Section 23. I/O Ports. 1.5.12 Port B I/O Pins (PTB7/ATD7-PTB0/ATD0) Port B is an 8-bit special function port that shares all eight pins with the Analog-to-Digital Converter (ADC). See Section 21. Analog-To-Digital Converter (ADC-15) and Section 23. I/O Ports. 1.5.13 Port C I/O Pins (PTC5-PTC0) PTC5-PTC3 and PTC1-PTC0 are general-purpose bidirectional I/O port pins. PTC2/MCLK is a special function port that shares its pin with the system clock which has a frequency equivalent to the system clock. See Section 23. I/O Ports. Advance Information 42 General Description For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. General Description Pin Assignments 1.5.14 Port D I/O Pins (PTD7-PTD0/ATD8) Port D is an 8-bit special-function port that shares seven of its pins with the Analog-to-Digital Converter module (ADC-15), one of its pins with the Timer Interface Module A (TIMA), and one more of its pins with the Timer Interface Module B (TIMB). See Section 18. Timer Interface Module A (TIMA), Section 19. Timer Interface Module B (TIMB), Section 21. Analog-To-Digital Converter (ADC-15) and Section 23. I/O Ports. Freescale Semiconductor, Inc... 1.5.15 Port E I/O Pins (PTE7/SPSCK-PTE0/TxD) Port E is an 8-bit special function port that shares two of its pins with the Timer Interface Module A (TIMA), four of its pins with the Serial Peripheral Interface module (SPI), and two of its pins with the Serial Communication Interface module (SCI). See Section 16. Serial Communications Interface (SCI), Section 17. Serial Peripheral Interface (SPI), Section 18. Timer Interface Module A (TIMA), and Section 23. I/O Ports. 1.5.16 Port F I/O Pins (PTF6-PTF0/TACH2) Port F is a 7-bit special function port that shares its pins with the Timer Interface Module B (TIMB). Six of its pins are shared with the Timer Interface Module A (TIMA-6). See Section 18. Timer Interface Module A (TIMA), Section 19. Timer Interface Module B (TIMB), and Section 23. I/O Ports. 1.5.17 Port G I/O Pins (PTG2/KBD2-PTG0/KBD0) Port G is a 3-bit special function port that shares all of its pins with the Keyboard Module (KBD). See Section 22. Keyboard Module (KBD) and Section 23. I/O Ports. 68HC908AZ32A -- Rev 0.0 MOTOROLA General Description For More Information On This Product, Go to: www.freescale.com Advance Information 43 Freescale Semiconductor, Inc. General Description 1.5.18 Port H I/O Pins (PTH1/KBD4-PTH0/KBD3) Port H is a 2-bit special-function port that shares all of its pins with the Keyboard Module (KBD). See Section 22. Keyboard Module (KBD) and Section 23. I/O Ports. 1.5.19 CAN Transmit Pin (CANTx) This pin is the digital output from the CAN module (CANTx). See Section 24. MSCAN Controller (MSCAN08). Freescale Semiconductor, Inc... 1.5.20 CAN Receive Pin (CANRx) This pin is the digital input to the CAN module (CANRx). See Section 24. MSCAN Controller (MSCAN08). Table 1-1. External Pins Summary Pin Name PTA7-PTA0 PTB7/ATD7-PTB0/ATD0 PTC5-PTC0 PTD7 PTD6/ATD14/TACLK ADC Channel Function General-Purpose I/O General-Purpose I/O ADC Channel General-Purpose I/O General Purpose I/O General-Purpose I/O ADC Channel/Timer External Input Clock General-Purpose I/O ADC Channel General-Purpose I/O ADC Channel/Timer External Input Clock General-Purpose I/O ADC Channel General-Purpose I/O SPI Clock Driver Type Dual State Dual State Dual State Dual State Dual State Hysteresis (1) Reset State Input Hi-Z Input Hi-Z Input Hi-Z Input Hi-Z Input Hi-Z No No No No No PTD5/ATD13 ADC Channel Dual State No Input Hi-Z PTD4/ATD12/TBCLK ADC Channel Dual State No Input Hi-Z PTD3/ATD11-PTD0/ATD8 ADC Channels PTE7/SPSCK Dual State Dual State Open Drain No Yes Input Hi-Z Input Hi-Z Advance Information 44 General Description For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. General Description Pin Assignments Table 1-1. External Pins Summary (Continued) Pin Name PTE6/MOSI PTE5/MISO PTE4/SS PTE3/TACH1 PTE2/TACH0 PTE1/RxD PTE0/TxD PTF6 PTF5/TBCH1-PTF4/TBCH0 PTF3/TACH5 PTF2/TACH4 PTF1/TACH3 PTF0/TACH2 Function General-Purpose I/O SPI Data Path General-Purpose I/O SPI Data Path General-Purpose I/O SPI Slave Select General-Purpose I/O Timer A Channel 1 General-Purpose I/O Timer A Channel 0 General-Purpose I/O SCI Receive Data General-Purpose I/O SCI Transmit Data General-Purpose I/O General-Purpose I/O/Timer B Channel General-Purpose I/O Timer A Channel 5 General-Purpose I/O Timer A Channel 4 General-Purpose I/O Timer A Channel 3 General-Purpose I/O Timer A Channel 2 General-Purpose I/O/ Keyboard Wakeup Pin General-Purpose I/O/ Keyboard Wakeup Pin Chip Power Supply Chip Ground CGM Analog Power Supply CGM Analog Ground Driver Type Dual State Open Drain Dual State Open Drain Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State Hysteresis (1) Reset State Input Hi-Z Input Hi-Z Input Hi-Z Input Hi-Z Input Hi-Z Input Hi-Z Input Hi-Z Input Hi-Z Input Hi-Z Input Hi-Z Input Hi-Z Input Hi-Z Input Hi-Z Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes Freescale Semiconductor, Inc... PTG2/KBD2-PTG0/KBD0 Dual State Yes Input Hi-Z PTH1/KBD4 -PTH0/KBD3 VDD VSS VDDA VSSA Dual State N/A N/A Yes N/A N/A Input Hi-Z N/A N/A 68HC908AZ32A -- Rev 0.0 MOTOROLA General Description For More Information On This Product, Go to: www.freescale.com Advance Information 45 Freescale Semiconductor, Inc. General Description Table 1-1. External Pins Summary (Continued) Pin Name VDDAREF AVSS/VREFL VREFH OSC1 OSC2 CGMXFC IRQ RST CANRx CANTx Function ADC Power Supply ADC Ground/ADC Reference Low Voltage A/D Reference High Voltage External Clock In External Clock Out PLL Loop Filter Cap External Interrupt Request Reset CAN Serial Input CAN Serial Output Driver Type N/A N/A Hysteresis (1) Reset State N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Output N/A N/A N/A N/A N/A N/A Yes No N/A Input Hi-Z Output N/A Input Hi-Z Output Low Input Hi-Z Output Freescale Semiconductor, Inc... 1. Hysteresis is not 100% tested but is typically a minimum of 300mV. Advance Information 46 General Description For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. General Description Pin Assignments Table 1-2. Clock Signal Naming Conventions Clock Signal Name CGMXCLK CGMOUT Bus Clock SPSCK TACLK TBCLK Description Buffered version of OSC1 from Clock Generation Module (CGM) PLL-based or OSC1-based clock output from Clock Generator Module (CGM) CGMOUT divided by two SPI serial clock External clock input for TIMA External clock input for TIMB Freescale Semiconductor, Inc... Table 1-3. Clock Source Summary Module ADC CAN COP CPU FLASH EEPROM RAM SPI SCI TIMA TIMB PIT SIM IRQ BRK LVI CGM Clock Source CGMXCLK or Bus Clock CGMXCLK or CGMOUT CGMXCLK Bus Clock Bus Clock CGMXCLK or Bus Clock Bus Clock Bus Clock/SPSCK CGMXCLK Bus Clock or PTD6/ATD14/TACLK Bus Clock or PTD4/TBCLK Bus Clock CGMOUT and CGMXCLK Bus Clock Bus Clock Bus Clock OSC1 and OSC2 68HC908AZ32A -- Rev 0.0 MOTOROLA General Description For More Information On This Product, Go to: www.freescale.com Advance Information 47 Freescale Semiconductor, Inc. General Description 1.6 Ordering Information This section contains instructions for ordering the 68HC908AZ32A. 1.6.1 MC Order Numbers Table 1-4. MC Order Numbers MC Order Number MC68HC908AZ32ACFU (64-Pin QFP) MC68HC908AZ32AVFU (64-Pin QFP) MC68HC908AZ32AMFU (64-Pin QFP) Operating Temperature Range -40C to + 85C -40C to + 105C -40C to + 125C Freescale Semiconductor, Inc... Advance Information 48 68HC908AZ32A -- Rev 0.0 General Description For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 2. Memory Map 2.1 Contents 2.2 2.3 2.4 2.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Additional Status and Control Registers . . . . . . . . . . . . . . . . . . 57 Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . . . . 59 Freescale Semiconductor, Inc... 2.2 Introduction The CPU08 can address 64K bytes of memory space. The memory map, shown in Figure 2-1, includes: * * * * * 32,256 Bytes of FLASH EEPROM 1024 Bytes of RAM 512 Bytes of EEPROM with Protect Option 52 Bytes of User-Defined Vectors 320 Bytes of Monitor ROM The following definitions apply to the memory map representation of reserved and unimplemented locations. * * Reserved -- Accessing a reserved location can have unpredictable effects on MCU operation. Unused -- These locations are reserved in the memory map for future use, accessing an unused location can have unpredictable effects on MCU operation. 68HC908AZ32A -- Rev 0.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com Advance Information 49 Freescale Semiconductor, Inc. Memory Map * Unimplemented -- Accessing an unimplemented location can cause an illegal address reset (within the constraints as outlined in the System Integration Module (SIM)). $0000 $004F $0050 I/O REGISTERS (80 BYTES) Freescale Semiconductor, Inc... $044F $0450 RAM (1024 BYTES) $04FF $0500 UNIMPLEMENTED (176 BYTES) $057F $0580 CAN CONTROL AND MESSAGE BUFFERS (128 BYTES) $07FF $0800 UNIMPLEMENTED (640 BYTES) $09FF $0A00 EEPROM (512 BYTES) $7FFF $8000 UNIMPLEMENTED (30,208 BYTES) $FDFF $FE00 $FE01 $FE02 FLASH (32,256 BYTES) SIM BREAK STATUS REGISTER (SBSR) SIM RESET STATUS REGISTER (SRSR) RESERVED Advance Information 50 Memory Map For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Memory Map Introduction $FE03 $FE04 SIM BREAK FLAG CONTROL REGISTER (SBFCR) $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FE11 $FE12 RESERVED (5 BYTES) FLASH CONTROL REGISTER (FLCR) RESERVED RESERVED BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BSCR) LVI STATUS REGISTER (LVISR) EEPROM DIVIDER HIGH NON-VOLATILE REGISTER (EEDIVHNVR) EEPROM DIVIDER LOW NON-VOLATILE REGISTER (EEDIVLNVR) Freescale Semiconductor, Inc... $FE19 $FE1A $FE1B $FE1C $FE1D $FE1E $FE1F $FE20 RESERVED (8 BYTES) EEPROM DIVIDER HIGH REGISTER (EEDIVH) EEPROM DIVIDER LOW REGISTER (EEDIVL) EEPROM NON-VOLATILE REGISTER (EENVR) EEPROM CONTROL REGISTER (EECR) RESERVED EEPROM ARRAY CONFIGURATION REGISTER (EEACR) $FF5F $FF60 MONITOR ROM (320 BYTES) $FF7F $FF80 $FF81 UNIMPLEMENTED (32 BYTES) FLASH BLOCK PROTECT REGISTER (FLBPR) 68HC908AZ32A -- Rev 0.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com Advance Information 51 Freescale Semiconductor, Inc. Memory Map $FF87 $FF88 $FF89 FLASH CONTROL REGISTER (FLCR) RESERVED (7 BYTES) $FF8F $FF90 RESERVED (7 BYTES) $FFBF $FFC0 UNIMPLEMENTED (48 BYTES) Freescale Semiconductor, Inc... $FFCB $FFCC RESERVED (12 BYTES) $FFFF VECTORS (52 BYTES) See Table 2-1 on page 59 Figure 2-1. Memory Map Advance Information 52 Memory Map For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Memory Map I/O Section 2.3 I/O Section Addresses $0000-$004F, shown in Figure 2-2, contain the I/O Data, Status and Control Registers. Addr. $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F Register Name Port A Data Register (PTA) Port B Data Register (PTB) Port C Data Register (PTC) Port D Data Register (PTD) Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 PTA7 PTB7 0 R PTD7 6 PTA6 PTB6 0 R PTD6 DDRA6 DDRB6 0 R DDRD6 PTE6 PTF6 0 R 0 R DDRE6 DDRF6 0 R 0 R 5 PTA5 PTB5 PTC5 PTD5 DDRA5 DDRB5 DDRC5 DDRD5 PTE5 PTF5 0 R 0 R DDRE5 DDRF5 0 R 0 R 4 PTA4 PTB4 PTC4 PTD4 DDRA4 DDRB4 DDRC4 DDRD4 PTE4 PTF4 0 R 0 R DDRE4 DDRF4 0 R 0 R 3 PTA3 PTB3 PTC3 PTD3 DDRA3 DDRB3 DDRC3 DDRD3 PTE3 PTF3 0 R 0 R DDRE3 DDRF3 0 R 0 R 2 PTA2 PTB2 PTC2 PTD2 DDRA2 DDRB2 DDRC2 DDR2 PTE2 PTF2 PTG2 0 R DDRE2 DDRF2 DDRG2 0 R 1 PTA1 PTB1 PTC1 PTD1 DDRA1 DDRB1 DDRC1 DDRD1 PTE1 PTF1 PTG1 PTH1 DDRE1 DDRF1 DDRG1 DDRH1 Bit 0 PTA0 PTB0 PTC0 PTD0 DDRA0 DDRB0 DDRC0 DDRD0 PTE0 PTF0 PTG0 PTH0 DDRE0 DDRF0 DDRG0 DDRH0 Freescale Semiconductor, Inc... Data Direction Register A Read: DDRA7 (DDRA) Write: Data Direction Register B Read: DDRB7 (DDRB) Write: Data Direction Register C Read: MCLKEN (DDRC) Write: Data Direction Register D Read: DDRD7 (DDRD) Write: Port E Data Register (PTE) Port F Data Register (PTF) Port G Data Register (PTG) Port H Data Register (PTH) Read: Write: Read: Write: Read: Write: Read: Write: PTE7 0 R 0 R 0 R Data Direction Register E Read: DDRE7 (DDRE) Write: Data Direction Register F Read: (DDRF) Write: Data Direction Register G Read: (DDRG) Write: Data Direction Register H Read: (DDRH) Write: 0 R 0 R 0 R Figure 2-2. I/O Data, Status and Control Registers (Sheet 1 of 5) 68HC908AZ32A -- Rev 0.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com Advance Information 53 Freescale Semiconductor, Inc. Memory Map Addr. $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 Register Name SPI Control Register (SPCR) Read: Write: Bit 7 SPRIE 6 R ERRIE R6 T6 ENSCI TCIE T8 TC 0 R6 T6 0 0 R 0 PLLF LOCK 5 SPMSTR OVRF R5 T5 TXINV SCRIE R SCRF 0 R5 T5 SCP1 0 R 0 4 CPOL MODF R4 T4 M ILIE R IDLE 0 R4 T4 SCP0 0 R 0 3 CPHA SPTE R3 T3 WAKE TE ORIE OR 0 R3 T3 R IRQF R KEYF 1 0 2 SPWOM MODFEN R2 T2 ILTY RE NEIE NF 0 R2 T2 SCR2 0 ACK 0 ACKK 1 0 1 SPE SPR1 R1 T1 PEN RWU FEIE FE BKF R1 T1 SCR1 IMASK Bit 0 SPTIE SPR0 R0 T0 PTY SBK PEIE PE RPF R0 T0 SCR0 MODE SPI Status and Control Read: SPRF Register (SPSCR) Write: SPI Data Register (SPDR) SCI Control Register 1 (SCC1) SCI Control Register 2 (SCC2) SCI Control Register 3 (SCC3) SCI Status Register 1 (SCS1) SCI Status Register 2 (SCS2) SCI Data Register (SCDR) SCI Baud Rate Register (SCBR) Read: Write: Read: Write: Read: Write: Read: Write: Read: SCTE Write: Read: Write: Read: Write: Read: Write: 0 R 0 R7 T7 0 0 R7 T7 LOOPS SCTIE R8 Freescale Semiconductor, Inc... IRQ Status and Control Read: Register (ISCR) Write: Keyboard Status and Control Read: Register (KBSCR) Write: PLL Control Register (PCTL) Read: Write: IMASKK MODEK 1 0 1 0 PLLIE PLLON ACQ MUL5 LVIRST TSTOP 0 BCS XLD MUL4 PLL Bandwidth Control Read: AUTO Register (PBWC) Write: PLL Programming Register Read: MUL7 (PPG) Write: Configuration Write-Once Read: LVISTOP Register (CONFIG-1) Write: Timer A Status and Control Register Read: (TASC) Write: Keyboard Interrupt Enable Register Read: (KBIER) Write: TOF 0 0 MUL6 R TOIE 0 VRS7 VRS6 COPRS PS2 KBIE2 VRS5 STOP PS1 KBIE1 VRS4 COPD PS0 KBIE0 LVIPWR SSREC 0 TRST KBIE4 0 R KBIE3 Figure 2-2. I/O Data, Status and Control Registers (Sheet 2 of 5) Advance Information 54 Memory Map For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Memory Map I/O Section Addr. $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F $0030 $0031 $0032 $0033 Register Name Timer A Counter Register Read: High (TACNTH) Write: Timer A Counter Register Read: Low (TACNTL) Write: Timer A Modulo Register Read: High (TAMODH) Write: Timer A Modulo Register Read: Low (TAMODL) Write: Timer A Channel 0 Status and Read: Control Register (TASC0) Write: Timer A Channel 0 Register Read: High (TACH0H) Write: Timer A Channel 0 Register Read: Low (TACH0L) Write: Timer A Channel 1 Status and Read: Control Register (TASC1) Write: Timer A Channel 1 Register Read: High (TACH1H) Write: Timer A Channel 1 Register Read: Low (TACH1L) Write: Timer A Channel 2 Status and Read: Control Register (TASC2) Write: Timer A Channel 2 Register Read: High (TACH2H) Write: Timer A Channel 2 Register Read: Low (TACH2L) Write: Timer A Channel 3 Status and Read: Control Register (TASC3) Write: Timer A Channel 3 Register Read: High (TACH3H) Write: Timer A Channel 3 Register Read: Low (TACH3L) Write: Timer A Channel 4 Status and Read: Control Register (TASC4) Write: Timer A Channel 4 Register High Read: (TACH4H) Write: Bit 7 Bit 15 R Bit 7 R Bit 15 Bit 7 CH0F 0 Bit 15 Bit 7 CH1F 0 Bit 15 Bit 7 CH2F 0 Bit 15 Bit 7 CH3F 0 Bit 15 Bit 7 CH4F 0 Bit 15 6 14 R 6 R 14 6 CH0IE 14 6 CH1IE 14 6 CH2IE 14 6 CH3IE 14 6 CH4IE 14 5 13 R 5 R 13 5 MS0B 13 5 0 R 13 5 MS2B 13 5 0 R 13 5 MS4B 13 4 12 R 4 R 12 4 MS0A 12 4 MS1A 12 4 MS2A 12 4 MS3A 12 4 MS4A 12 3 11 R 3 R 11 3 ELS0B 11 3 ELS1B 11 3 ELS2B 11 3 ELS3B 11 3 ELS4B 11 2 10 R 2 R 10 2 ELS0A 10 2 ELS1A 10 2 ELS2A 10 2 ELS3A 10 2 ELS4A 10 1 9 R 1 R 9 1 TOV0 9 1 TOV1 9 1 TOV2 9 1 TOV3 9 1 TOV4 9 Bit 0 Bit 8 R Bit 0 R Bit 8 Bit 0 CH0MAX Bit 8 Bit 0 CH1MAX Bit 8 Bit 0 CH2MAX Bit 8 Bit 0 CH3MAX Bit 8 Bit 0 CH4MAX Bit 8 Freescale Semiconductor, Inc... Figure 2-2. I/O Data, Status and Control Registers (Sheet 3 of 5) 68HC908AZ32A -- Rev 0.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com Advance Information 55 Freescale Semiconductor, Inc. Memory Map Addr. $0034 $0035 $0036 $0037 $0038 $0039 $003A $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 Register Name Timer A Channel 4 Register Low Read: (TACH4L) Write: Timer A Channel 5 Status and Read: Control Register (TASC5) Write: Timer A Channel 5 Register Read: High (TACH5H) Write: Timer A Channel 5 Register Read: Low (TACH5L) Write: Bit 7 Bit 7 CH5F 0 Bit 15 Bit 7 6 6 CH5IE 14 6 AIEN AD6 R ADIV1 TOIE 14 R 6 R 14 6 CH0IE 14 6 CH1IE 14 6 5 5 0 R 13 5 ADCO AD5 R ADIV0 TSTOP 13 R 5 R 13 5 MS0B 13 5 0 R 13 5 4 4 MS5A 12 4 ADCH4 AD4 R ADICLK 0 TRST 12 R 4 R 12 4 MS0A 12 4 MS1A 12 4 3 3 ELS5B 11 3 ADCH3 AD3 R 0 R 0 R 11 R 3 R 11 3 ELS0B 11 3 ELS1B 11 3 2 2 ELS5A 10 2 ADCH2 AD2 R 0 R PS2 10 R 2 R 10 2 ELS0A 10 2 ELS1A 10 2 1 1 TOV5 9 1 ADCH1 AD1 R 0 R PS1 9 R 1 R 9 1 TOV0 9 1 TOV1 9 1 Bit 0 Bit 0 CH5MAX Bit 8 Bit 0 ADCH0 AD0 R 0 R PS0 Bit 8 R Bit 0 R Bit 8 Bit 0 CH0MAX Bit 8 Bit 0 CH1MAX Bit 8 Bit 0 Freescale Semiconductor, Inc... Analog-to-Digital Status and Control Read: COCO Register (ADSCR) Write: R Analog-to-Digital Data Register Read: (ADR) Write: AD7 R Analog-to-Digital Input Clock Read: ADIV2 Register (ADICLK) Write: Timer B Status and Control Register Read: (TBSCR) Write: Timer B Counter Register High Read: (TBCNTH) Write: Timer B Counter Register Low Read: (TBCNTL) Write: Timer B Modulo Register High Read: (TBMODH) Write: Timer B Modulo Register Low Read: (TBMODL) Write: Timer B CH0 Status and Control Read: Register (TBSC0) Write: Timer B CH0 Register High Read: (TBCH0H) Write: Timer B CH0 Register Low Read: (TBCH0L) Write: Timer B CH1 Status and Control Read: Register (TBSC1) Write: Timer B CH1 Register High Read: (TBCH1H) Write: Timer B CH1 Register Low Read: (TBCH1L) Write: TOF 0 Bit 15 R Bit 7 R Bit 15 Bit 7 CH0F 0 Bit 15 Bit 7 CH1F 0 Bit 15 Bit 7 $0048 $0049 $004A Figure 2-2. I/O Data, Status and Control Registers (Sheet 4 of 5) Advance Information 56 Memory Map For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Memory Map Additional Status and Control Registers Addr. $004B $004C Register Name PIT Status and Control Register Read: (PSC) Write: PIT Counter Register High Read: (PCNTH) Write: Read: Write: Bit 7 POF 0 Bit 15 Bit 7 6 POIE 14 6 5 PSTOP 13 5 4 0 PRST 12 4 3 0 11 3 2 PPS2 10 2 1 PPS1 9 1 Bit 0 PPS0 Bit 8 Bit 0 $004D PIT Counter Register Low (PCNTL) $004E PIT Modulo Register High Read: (PMODH) Write: Read: Write: Bit 15 Bit 7 14 6 13 5 12 4 11 3 10 2 9 1 Bit 8 Bit 0 Freescale Semiconductor, Inc... $004F PIT Modulo Register Low (PMODL) = Unimplemented R = Reserved Figure 2-2. I/O Data, Status and Control Registers (Sheet 5 of 5) 2.4 Additional Status and Control Registers Selected addresses in the range $FE00 to $FFCB contain additional Status and Control registers as shown in Figure 2-3. A noted exception is the COP Control Register (COPCTL) at address $FFFF. Addr. $FE00 Register Name SIM Break Status Register Read: (SBSR) Write: Read: Write: R R 14 6 R R 13 5 R EEMONSEC Bit 7 R POR 6 R PIN 5 R COP 4 R ILOP 3 R ILAD 2 R 0 1 BW 0 LVI Bit 0 R 0 $FE01 SIM Reset Status Register (SRSR) $FE03 $FE09 $FE0C $FE0D SIM Break Flag Control Register Read: BCFE (SBFCR) Write: Configuration Write-Once Register Read: EEDIVCLK (CONFIG-2) Write: Break Address Register High Read: (BRKH) Write: Break Address Register Low Read: (BRKL) Write: Bit 15 Bit 7 R AZ32A R 11 3 R R 10 2 R R 9 1 R R Bit 8 Bit 0 12 4 Figure 2-3. Additional Status and Control Registers (Sheet 1 of 2) 68HC908AZ32A -- Rev 0.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com Advance Information 57 Freescale Semiconductor, Inc. Memory Map Addr. $FE0E $FE0F $FE10 $FE11 $FE1A $FE1B Register Name Bit 7 6 BRKA 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Break Status and Control Read: BRKE Register (BRKSCR) Write: LVI Status Register (LVISR) Read: LVIOUT Write: EEDIV Hi Non-volatile Register Read: EEDIVSECD (EEDIVHNVR) Write: EEDIV Lo Non-volatile Register Read: EEDIV7 (EEDIVLNVR) Write: EEDIV Divider High Register Read: EEDIVSECD (EEDIVH) Write: EEDIV Divider Low Register Read: EEDIV7 (EEDIVL) Write: R EEDIV6 0 R EEDIV5 0 R EEDIV4 0 R EEDIV3 0 EEDIV10 EEDIV9 EEDIV2 EEDIV1 EEDIV8 EEDIV0 EEDIV8 EEDIV0 EEBP0 EEPGM EEBP0 Freescale Semiconductor, Inc... EEDIV10 EEDIV9 EEDIV2 EEBP2 EELAT EEBP2 EEDIV1 EEBP1 AUTO EEBP1 EEDIV6 EEDIV5 EEDIV4 EEDIV3 $FE1C EEPROM Nonvolatile Register Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3 (EENVR) Write: Read: Write: UNUSED 0 EEOFF EERAS1 EERAS0 $FE1D EEPROM Control Register (EECR) $FE1F $FF80 $FF88 EEPROM Array Configuration Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3 Register (EEACR) Write: FLASH Block Protect Register Read: (FLBPR) Write: FLASH Control Register Read: (FLCR) Write: Read: Write: BPR7 0 BPR6 0 BPR5 0 BPR4 0 BPR3 HVEN BPR2 VERF BPR1 ERASE BPR0 PGM $FFFF COP Control Register (COPCTL) LOW BYTE OF RESET VECTOR WRITING TO $FFFF CLEARS COP COUNTER = Unimplemented R = Reserved Figure 2-3. Additional Status and Control Registers (Sheet 2 of 2) Advance Information 58 Memory Map For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Memory Map Vector Addresses and Priority 2.5 Vector Addresses and Priority Addresses in the range $FFCC to $FFFF contain the user-specified vector locations. The vector addresses are shown in Table 2-1. It is recommended that all vector addresses are defined. Table 2-1. Vector Addresses Address Lowest Priority $FFCC $FFCD $FFCE $FFCF $FFD0 $FFD1 $FFD2 $FFD3 $FFD4 $FFD5 $FFD6 $FFD7 $FFD8 $FFD9 $FFDA $FFDB $FFDC $FFDD $FFDE $FFDF $FFE0 $FFE1 $FFE2 $FFE3 $FFE4 Vector Description TIMA Channel 5 Vector (High) TIMA Channel 5 Vector (Low) TIMA Channel 4 Vector (High) TIMA Channel 4 Vector (Low) ADC Vector (High) ADC Vector (Low) Keyboard Vector (High) Keyboard Vector (Low) SCI Transmit Vector (High) SCI Transmit Vector (Low) SCI Receive Vector (High) SCI Receive Vector (Low) SCI Error Vector (High) SCI Error Vector (Low) CAN Transmit Vector (High) CAN Transmit Vector (Low) CAN Receive Vector (High) CAN Receive Vector (Low) CAN Error Vector (High) CAN Error Vector (Low) CAN Wakeup Vector (High) CAN Wakeup Vector (Low) SPI Transmit Vector (High) SPI Transmit Vector (Low) SPI Receive Vector (High) Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information Memory Map For More Information On This Product, Go to: www.freescale.com 59 Freescale Semiconductor, Inc. Memory Map Table 2-1. Vector Addresses Address $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE $FFEF $FFF0 $FFF1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE Vector Description SPI Receive Vector (Low) TIMB Overflow Vector (High) TIMB Overflow Vector (Low) TIMB CH1 Vector (High) TIMB CH1 Vector (Low) TIMB CH0 Vector (High) TIMB CH0 Vector (Low) TIMA Overflow Vector (High) TIMA Overflow Vector (Low) TIMA CH3 Vector (High) TIMA CH3 Vector (Low) TIMA CH2 Vector (High) TIMA CH2 Vector (Low) TIMA CH1 Vector (High) TIMA CH1 Vector (Low) TIMA CH0 Vector (High) TIMA CH0 Vector (Low) PIT Vector (High) PIT Vector (Low) PLL Vector (High) PLL Vector (Low) IRQ1 Vector (High) IRQ1 Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low) Freescale Semiconductor, Inc... Highest Priority $FFFF Advance Information 60 Memory Map For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 3. RAM 3.1 Contents 3.2 3.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Freescale Semiconductor, Inc... 3.2 Introduction This section describes the 1024 bytes of random-access memory (RAM). 3.3 Functional Description Addresses $0050 through $044F are RAM locations. The location of the stack RAM is programmable with the reset stack pointer instruction (RSP). The 16-bit stack pointer allows the stack RAM to be anywhere in the 64K-byte memory space. NOTE: For correct operation, the stack pointer must point only to RAM locations. Within page zero are 176 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for input/output (I/O) control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access all page zero RAM locations efficiently. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. 68HC908AZ32A -- Rev 0.0 MOTOROLA RAM For More Information On This Product, Go to: www.freescale.com Advance Information 61 Freescale Semiconductor, Inc. RAM NOTE: For M68HC05, M6805, and M146805 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU could overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Freescale Semiconductor, Inc... Advance Information 62 RAM For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 4. FLASH Memory 4.1 Contents 4.2 4.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Freescale Semiconductor, Inc... 4.2 FLASH Control and Block Protect Registers . . . . . . . . . . . . . . 64 4.4.1 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.2 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . .66 4.5 4.6 4.7 4.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 69 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 70 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4.9.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.9.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.2 Introduction This section describes the operation of the embedded FLASH memory. This memory can be read, programmed and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. 68HC908AZ32A -- Rev 0.0 MOTOROLA FLASH Memory For More Information On This Product, Go to: www.freescale.com Advance Information 63 Freescale Semiconductor, Inc. FLASH Memory 4.3 Functional Description The FLASH memory is an array of 32,256 bytes with one byte of block protection and an additional 52 bytes of user vectors. An erased bit reads as a logic 1 and a programmed bit reads as a logic 0. Memory in the FLASH array is organized into rows within pages. There are two rows of memory per page with 64 bytes per row. The minimum erase block size is a single page,128 bytes. Programming is performed on a per-row basis, 64 bytes at a time. Program and erase operations are facilitated through control bits in the FLASH Control Register (FLCR). Details for these operations appear later in this section. The FLASH memory map consists of: * * * * $8000-$FDFF: User Memory (32,256 bytes) $FF80: FLASH Block Protect Register (FLBPR) $FF88: FLASH Control Register (FLCR) $FFCC-$FFFF: these locations are reserved for user-defined interrupt and reset vectors (Please see Vector Addresses and Priority on page 59 for details) Freescale Semiconductor, Inc... Programming tools are available from Motorola. Contact your local Motorola representative for more information. NOTE: A security feature prevents viewing of the FLASH contents.(1) 4.4 FLASH Control and Block Protect Registers The FLASH array has two registers that control its operation, the FLASH Control Register (FLCR) and the FLASH Block Protect Register (FLBPR). 1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users. Advance Information 64 FLASH Memory For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. FLASH Memory FLASH Control and Block Protect Registers 4.4.1 FLASH Control Register The FLASH Control Register (FLCR) controls FLASH program and erase operations. Address: $FF88 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 HVEN MASS ERASE PGM 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 4-1. FLASH Control Register (FLCR) HVEN -- High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS -- Mass Erase Control Bit Setting this read/write bit configures the FLASH array for mass or page erase operation. 1 = Mass erase operation selected 0 = Page erase operation selected ERASE -- Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be set at the same time. 1 = Erase operation selected 0 = Erase operation unselected 68HC908AZ32A -- Rev 0.0 MOTOROLA FLASH Memory For More Information On This Product, Go to: www.freescale.com Advance Information 65 Freescale Semiconductor, Inc. FLASH Memory PGM -- Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation unselected 4.4.2 FLASH Block Protect Register The FLASH Block Protect Register (FLBPR) is implemented as a byte within the FLASH memory and therefore can only be written during a FLASH programming sequence. The value in this register determines the starting location of the protected range within the FLASH memory. Address: $FF80 Bit 7 Read: BPR7 Write: BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 4-2. FLASH Block Protect Register (FLBPR) FLBPR[7:0] -- Block Protect Register Bit7 to Bit0 These eight bits represent bits [14:7] of a 16-bit memory address. Bit15 is logic 1 and bits [6:0] are logic 0s. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. FLASH is protected from this start address to the end of FLASH memory at $FFFF. With this mechanism, the protect start address can be $XX00 and $XX80 (128 byte page boundaries) within the FLASH array. 16-bit memory address Start address of FLASH block protect 1 FLBPR value 0 0 0 0 0 0 0 Figure 4-3. FLASH Block Protect Start Address Advance Information 66 FLASH Memory For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. FLASH Memory FLASH Control and Block Protect Registers FLASH Protected Ranges: FLBPR[7:0] $FF $FE $FD Protected Range No Protection $FF00 - $FFFF $FE80 - $FFFF Freescale Semiconductor, Inc... $0B $0A $09 $08 $8580 - $FFFF $8500 - $FFFF $8480 - $FFFF $8400 - $FFFF $04 $03 $02 $01 $00 $8200 - $FFFF $8180 - $FFFF $8100 - $FFFF $8080 - $FFFF $8000 - $FFFF Decreasing the value in FLBPR by one increases the protected range by one page (128 bytes). However, programming the block protect register with $FE protects a range twice that size, 256 bytes, in the corresponding array. $FE means that locations $FF00-$FFFF are protected in FLASH. The FLASH memory does not exist at some locations. The block protection range configuration is unaffected if FLASH memory does not exist in that range. Refer to the memory map and make sure that the desired locations are protected. 68HC908AZ32A -- Rev 0.0 MOTOROLA FLASH Memory For More Information On This Product, Go to: www.freescale.com Advance Information 67 Freescale Semiconductor, Inc. FLASH Memory 4.5 FLASH Block Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by using the FLASH Block Protection Register (FLBPR). FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends at the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit can not be set in either ERASE or PROGRAM operations. Freescale Semiconductor, Inc... NOTE: In performing a program or erase operation, the FLASH Block Protect Register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit. When the FLASH Block Protect Register is programmed with all 0's, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1's), the entire memory is accessible for program and erase. When bits within FLBPR are programmed (logic 0), they lock a block of memory address ranges as shown in FLASH Block Protect Register on page 66. If FLBPR is programmed with any value other than $FF, the protected block of FLASH memory can not be erased or programmed. NOTE: The vector locations and the FLASH Block Protect Registers are located in the same page. FLBPR is not protected with special hardware or software; therefore, if this page is not protected by FLBPR and the vector locations are erased by either a page or a mass erase operation, FLBPR will also get erased. Advance Information 68 FLASH Memory For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. FLASH Memory FLASH Mass Erase Operation 4.6 FLASH Mass Erase Operation Use this step-by-step procedure to erase the entire FLASH memory to read as logic 1: 1. Set both the ERASE bit and the MASS bit in the FLASH Control Register (FLCR). 2. Read the FLASH Block Protect Register (FLBPR). 3. Write to any FLASH address within the FLASH array with any data. Freescale Semiconductor, Inc... NOTE: If the address written to in Step 3 is within address space protected by the FLASH Block Protect Register (FLBPR), no erase will occur. 4. Wait for a time, tNVS. 5. Set the HVEN bit. 6. Wait for a time, tMERASE. 7. Clear the ERASE bit. 8. Wait for a time, t NVHL. 9. Clear the HVEN bit. 10. Wait for a time, tRCV, after which the memory can be accessed in normal read mode. NOTE: A. Programming and erasing of FLASH locations can not be performed by code being executed from the same FLASH array. B. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Care must be taken however to ensure that these operations do not access any address within the FLASH array memory space such as the COP Control Register (COPCTL) at $FFFF. C. It is highly recommended that interrupts be disabled during program/erase operations. 68HC908AZ32A -- Rev 0.0 MOTOROLA FLASH Memory For More Information On This Product, Go to: www.freescale.com Advance Information 69 Freescale Semiconductor, Inc. FLASH Memory 4.7 FLASH Page Erase Operation Use this step-by-step procedure to erase a page (128 bytes) of FLASH memory to read as logic 1: 1. Set the ERASE bit and clear the MASS bit in the FLASH Control Register (FLCR). 2. Read the FLASH Block Protect Register (FLBPR). 3. Write any data to any FLASH address within the address range of the page (128 byte block) to be erased. 4. Wait for time, tNVS. 5. Set the HVEN bit. 6. Wait for time, tERASE. 7. Clear the ERASE bit. 8. Wait for time, t NVH. 9. Clear the HVEN bit. 10. Wait for a time, tRCV, after which the memory can be accessed in normal read mode. Freescale Semiconductor, Inc... NOTE: A. Programming and erasing of FLASH locations can not be performed by code being executed from the same FLASH array. B. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Care must be taken however to ensure that these operations do not access any address within the FLASH array memory space such as the COP Control Register (COPCTL) at $FFFF. C. It is highly recommended that interrupts be disabled during program/erase operations. Advance Information 70 FLASH Memory For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. FLASH Memory FLASH Program Operation 4.8 FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes with address ranges as follows: * * * * $XX00 to $XX3F $XX40 to $XX7F $XX80 to $XXBF $XXC0 to $XXFF Freescale Semiconductor, Inc... During the programming cycle, make sure that all addresses being written to fit within one of the ranges specified above. Attempts to program addresses in different row ranges in one programming cycle will fail. Use this step-by-step procedure to program a row of FLASH memory. NOTE: In order to avoid program disturbs, the row must be erased before any byte on that row is programmed. 1. Set the PGM bit in the FLASH Control Register (FLCR). This configures the memory for program operation and enables the latching of address and data programming. 2. Read the FLASH Block Protect Register (FLBPR). 3. Write to any FLASH address within the row address range desired with any data. 4. Wait for time, tNVS. 5. Set the HVEN bit. 6. Wait for time, tPGS. 7. Write data byte to the FLASH address to be programmed. 8. Wait for time, t PROG. 9. Repeat step 7 and 8 until all the bytes within the row are programmed. 10. Clear the PGM bit. 11. Wait for time, tNVH. 68HC908AZ32A -- Rev 0.0 MOTOROLA FLASH Memory For More Information On This Product, Go to: www.freescale.com Advance Information 71 Freescale Semiconductor, Inc. FLASH Memory 12. Clear the HVEN bit. 13. Wait for a time, tRCV, after which the memory can be accessed in normal read mode. The FLASH Programming Algorithm Flowchart is shown in Figure 4-4. NOTE: A. Programming and erasing of FLASH locations can not be performed by code being executed from the same FLASH array. B. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Care must be taken however to ensure that these operations do not access any address within the FLASH array memory space such as the COP Control Register (COPCTL) at $FFFF. C. It is highly recommended that interrupts be disabled during program/erase operations. D. Do not exceed t PROG maximum or tHV maximum. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tNVS+ tNVH + tPGS + (tPROGX 64) tHV max. Please also see FLASH Memory Characteristics on page 455. E. The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing the PGM bit (step 7 to step 10) must not exceed the maximum programming time, tPROG max. F. Be cautious when programming the FLASH array to ensure that nonFLASH locations are not used as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm. This applies particularly to: * $FFCC-$FFFF: User Vector Area Freescale Semiconductor, Inc... Advance Information 72 68HC908AZ32A -- Rev 0.0 FLASH Memory For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. FLASH Memory FLASH Program Operation 1 Set PGM bit Algorithm for programming a row (64 bytes) of FLASH memory 2 Read the FLASH block protect register 3 Write any data to any FLASH address within the row address range desired 4 Freescale Semiconductor, Inc... Wait for a time, tnvs 5 Set HVEN bit 6 Wait for a time, tpgs 7 Write data to the FLASH address to be programmed 8 Wait for a time, tPROG Completed programming this row? N Y NOTE: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step 10) must not exceed the maximum programming time, tPROG max. This row program algorithm assumes the row/s to be programmed are initially erased. 10 Clear PGM bit 11 Wait for a time, tnvh 12 Clear HVEN bit 13 Wait for a time, trcv End of programming Figure 4-4. FLASH Programming Algorithm Flowchart 68HC908AZ32A -- Rev 0.0 MOTOROLA FLASH Memory For More Information On This Product, Go to: www.freescale.com Advance Information 73 Freescale Semiconductor, Inc. FLASH Memory 4.9 Low-Power Modes The WAIT and STOP instructions will place the MCU in low power consumption standby modes. 4.9.1 WAIT Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly; however, no memory activity will take place since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH. Wait mode will suspend any FLASH program/erase operations and leave the memory in a Standby Mode. Freescale Semiconductor, Inc... 4.9.2 STOP Mode Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly; however, no memory activity will take place since the CPU is inactive. The STOP instruction should not be executed while performing a program or erase operation on the FLASH. Stop mode will suspend any FLASH program/erase operations and leave the memory in a Standby Mode. NOTE: Standby Mode is the power saving mode of the FLASH module, in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is minimum. Advance Information 74 FLASH Memory For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 5. EEPROM 5.1 Contents 5.2 5.3 5.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 EEPROM Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Freescale Semiconductor, Inc... 5.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.5.1 EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.5.2 EEPROM Timebase Requirements . . . . . . . . . . . . . . . . . . . 78 5.5.3 EEPROM Program/Erase Protection . . . . . . . . . . . . . . . . . . 79 5.5.4 EEPROM Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.5.5 EEPROM Programming and Erasing . . . . . . . . . . . . . . . . . . 80 5.6 EEPROM Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 84 5.6.1 EEPROM Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.6.2 EEPROM Array Configuration Register . . . . . . . . . . . . . . . .87 5.6.3 EEPROM Nonvolatile Register. . . . . . . . . . . . . . . . . . . . . . .89 5.6.4 EEPROM Timebase Divider Register . . . . . . . . . . . . . . . . . 89 5.6.5 EEPROM Timebase Divider Non-Volatile Register . . . . . . . 91 5.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 5.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.2 Introduction This section describes the 512 bytes of electrically erasable programmable read-only memory (EEPROM) residing at address range $0800 to $09FF. 68HC908AZ32A -- Rev 0.0 MOTOROLA EEPROM For More Information On This Product, Go to: www.freescale.com Advance Information 75 Freescale Semiconductor, Inc. EEPROM 5.3 Features Features of the EEPROM include the following: * * * * * * 512 bytes Non-Volatile Memory Byte, Block, or Bulk Erasable Non-Volatile EEPROM Configuration and Block Protection Options On-chip Charge Pump for Programming/Erasing Security Option AUTO Bit Driven Programming/Erasing Time Feature Freescale Semiconductor, Inc... Advance Information 76 68HC908AZ32A -- Rev 0.0 EEPROM For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. EEPROM EEPROM Register Summary 5.4 EEPROM Register Summary The EEPROM Register Summary is shown in Figure 5-1. Addr. Register Name Bit 7 6 R 5 R 4 R 3 R 2 EEDIV10 1 EEDIV9 Bit 0 EEDIV8 $FE10 Read: EEDIV Non-volatile EEDIVSECD Register High Write: (EEDIVHNVR)* Reset: Read: EEDIV Non-volatile EEDIV7 Register Low Write: (EEDIVLNVR)* Reset: Read: EE Divider Register High Write: (EEDIVH) Reset: Read: EEDIVSECD Unaffected by reset; $FF when blank EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0 Freescale Semiconductor, Inc... $FE11 Unaffected by reset; $FF when blank 0 0 0 0 EEDIV10 Contents of EEDIVHNVR ($FE10), Bits [6:3] = 0 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0 EEDIV9 EEDIV8 $FE1A $FE1B EEDIV7 EE Divider Register Low Write: (EEDIVL) Reset: Contents of EEDIVLNVR ($FE11) EEBP0 $FE1C Read: EEPROM Non-volatile UNUSED UNUSED UNUSED EEPRTCT EEBP3 EEBP2 EEBP1 Register Write: (EENVR)* Reset: Unaffected by reset; $FF when blank; factory programmed $F0 Read: EEPROM Control UNUSED Register Write: (EECR) Reset: 0 0 EEOFF 0 0 EERAS1 0 EERAS0 0 EELAT 0 AUTO 0 EEBP1 EEPGM 0 EEBP0 $FE1D $FE1F Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3 EEBP2 EEPROM Array Configuration Register Write: (EEACR) Reset: Contents of EENVR ($FE1C) * Non-volatile EEPROM register; write by programming. = Unimplemented R = Reserved UNUSED = Unused Figure 5-1. EEPROM Register Summary 68HC908AZ32A -- Rev 0.0 MOTOROLA EEPROM For More Information On This Product, Go to: www.freescale.com Advance Information 77 Freescale Semiconductor, Inc. EEPROM 5.5 Functional Description The 512 bytes of EEPROM are located at $0800-$09FF and can be programmed or erased without an additional external high voltage supply. The program and erase operations are enabled through the use of an internal charge pump. For each byte of EEPROM, the write/erase endurance is 10,000 cycles. 5.5.1 EEPROM Configuration The 8-bit EEPROM Non-Volatile Register (EENVR) and the 16-bit EEPROM Timebase Divider Non-Volatile Register (EEDIVNVR) contain the default settings for the following EEPROM configurations: * * * EEPROM Timebase Reference EEPROM Security Option EEPROM Block Protection Freescale Semiconductor, Inc... EENVR and EEDIVNVR are non-volatile EEPROM registers. They are programmed and erased in the same way as EEPROM bytes. The contents of these registers are loaded into their respective volatile registers during a MCU reset. The values in these read/write volatile registers define the EEPROM configurations. For EENVR, the corresponding volatile register is the EEPROM Array Configuration Register (EEACR). For the EEDIVNCR (two 8-bit registers: EEDIVHNVR and EEDIVLNVR), the corresponding volatile register is the EEPROM Divider Register (EEDIV: EEDIVH and EE DIVL). 5.5.2 EEPROM Timebase Requirements A 35s timebase is required by the EEPROM control circuit for program and erase of EEPROM content. This timebase is derived from dividing the CGMXCLK or bus clock (selected by EEDIVCLK bit in CONFIG-2 Register) using a timebase divider circuit controlled by the 16-bit EEPROM Timebase Divider EEDIV Register (EEDIVH and EEDIVL). Advance Information 78 EEPROM For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. EEPROM Functional Description As the CGMXCLK or bus clock is user selected, the EEPROM Timebase Divider Register must be configured with the appropriate value to obtain the 35 s. The timebase divider value is calculated by using the following formula: EEDIV= INT[Reference Frequency(Hz) x 35 x10-6 +0.5] This value is written to the EEPROM Timebase Divider Register (EEDIVH and EEDIVL) or programmed into the EEPROM Timebase Divider Non-Volatile Register prior to any EEPROM program or erase operations(see EEPROM Configuration on page 78 and EEPROM Timebase Requirements on page 78). Freescale Semiconductor, Inc... 5.5.3 EEPROM Program/Erase Protection The EEPROM has a special feature that designates the 16 bytes of addresses from $08F0 to $08FF to be permanently secured. This program/erase protect option is enabled by programming the EEPRTCT bit in the EEPROM Non-Volatile Register (EENVR) to a logic zero. Once the EEPRTCT bit is programmed to 0 for the first time: * * * * * Programming and erasing of secured locations $08F0 to $08FF is permanently disabled. Secured locations $08F0 to $08FF can be read as normal. Programming and erasing of EENVR is permanently disabled. Bulk and Block Erase operations are disabled for the unprotected locations $0800-$08EF, $0900-$09FF. Single byte program and erase operations are still available for locations $0800-$08EF and $0900-$09FF for all bytes that are not protected by the EEPROM Block Protect EEBPx bits (see EEPROM Block Protection on page 80 and EEPROM Array Configuration Register on page 87) NOTE: Once armed, the protect option is permanently enabled. As a consequence, all functions in the EENVR will remain in the state they were in immediately before the security was enabled. 68HC908AZ32A -- Rev 0.0 MOTOROLA EEPROM For More Information On This Product, Go to: www.freescale.com Advance Information 79 Freescale Semiconductor, Inc. EEPROM 5.5.4 EEPROM Block Protection The 512 bytes of EEPROM are divided into four 128-byte blocks. Each of these blocks can be protected from erase/program operations by setting the EEBPx bit in the EENVR. Table 5-1 shows the address ranges for the blocks. Table 5-1. EEPROM Array Address Blocks Block Number (EEBPx) EEBP0 EEBP1 EEBP2 EEBP3 Address Range $0800-$087F $0880-$08FF $0900-$097F $0980-$09FF Freescale Semiconductor, Inc... These bits are effective after a reset or a upon read of the EENVR register. The block protect configuration can be modified by erasing/programming the corresponding bits in the EENVR register and then reading the EENVR register. Please see EEPROM Array Configuration Register on page 87 for more information. NOTE: Once EEDIVSECD in the EEDIVHNVR is programmed to 0 and after a system reset, the EEDIV security feature is permanently enabled because the EEDIVSECD bit in the EEDIVH is always loaded with 0 thereafter. Once this security feature is armed, erase and program mode are disabled for EEDIVHNVR and EEDIVLNVR. Modifications to the EEDIVH and EEDIVL registers are also disabled. Therefore, be cautious on programming a value into the EEDIVHNVR. 5.5.5 EEPROM Programming and Erasing The unprogrammed or erase state of an EEPROM bit is a logic 1. The factory default for all bytes within the EEPROM array is $FF. The programming operation changes an EEPROM bit from logic 1 to logic 0 (programming cannot change a bit from logic 0 to a logic 1). In a single programming operation, the minimum EEPROM programming size is one bit; the maximum is eight bits (one byte). Advance Information 80 EEPROM For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. EEPROM Functional Description The erase operation changes an EEPROM bit from logic 0 to logic 1. In a single erase operation, the minimum EEPROM erase size is one byte; the maximum is the entire EEPROM array. The EEPROM can be programmed such that one or multiple bits are programmed (written to a logic 0) at a time. However, the user may never program the same bit location more than once before erasing the entire byte. In other words, the user is not allowed to program a logic 0 to a bit that is already programmed (bit state is already logic 0). For some applications it might be advantageous to track more than 10K events with a single byte of EEPROM by programming one bit at a time. For that purpose, a special selective bit programming technique is available. An example of this technique is illustrated in Table 5-2. Table 5-2. Example Selective Bit Programming Description Description Original state of byte (erased) First event is recorded by programming bit position 0 Second event is recorded by programming bit position 1 Third event is recorded by programming bit position 2 Fourth event is recorded by programming bit position 3 Events five through eight are recorded in a similar fashion Program Data in Binary n/a 1111:1110 1111:1101 1111:1011 1111:0111 Result in Binary 1111:1111 1111:1110 1111:1100 1111:1000 1111:0000 Freescale Semiconductor, Inc... Note that none of the bit locations are actually programmed more than once although the byte was programmed eight times. When this technique is utilized, a program/erase cycle is defined as multiple program sequences (up to eight) to a unique location followed by a single erase operation. Program/Erase Using AUTO Bit An additional feature available for EEPROM program and erase operations is the AUTO mode. When enabled, AUTO mode will activate an internal timer that will automatically terminate the program/erase cycle and clear the EEPGM bit. Please see EEPROM Programming on page 82, EEPROM Erasing on page 83 and EEPROM Control Register on page 85 for more information. Advance Information EEPROM For More Information On This Product, Go to: www.freescale.com 81 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. EEPROM EEPROM Programming The unprogrammed or erase state of an EEPROM bit is a logic 1. Programming changes the state to a logic 0. Only EEPROM bytes in the non-protected blocks and the EENVR register can be programmed. Use the following procedure to program a byte of EEPROM: 1. Clear EERAS1 and EERAS0 and set EELAT in the EECR.(A) NOTE: If using the AUTO mode, also set the AUTO bit during Step 1. 2. Write the desired data to the desired EEPROM address.(B) 3. Set the EEPGM bit.(C) Go to Step 7 if AUTO is set. 4. Wait for time, tEEPGM, to program the byte. 5. Clear EEPGM bit. 6. Wait for time, tEEFPV, for the programming voltage to fall. Go to Step 8. 7. Poll the EEPGM bit until it is cleared by the internal timer.(D) 8. Clear EELAT bits.(E) Freescale Semiconductor, Inc... NOTE: A. EERAS1 and EERAS0 must be cleared for programming. Setting the EELAT bit configures the address and data buses to latch data for programming the array. Only data with a valid EEPROM address will be latched. If EELAT is set, other writes to the EECR will be allowed after a valid EEPROM write. B. If more than one valid EEPROM write occurs, the last address and data will be latched overriding the previous address and data. Once data is written to the desired address, do not read EEPROM locations other than the written location. (Reading an EEPROM location returns the latched data and causes the read address to be latched). C. The EEPGM bit cannot be set if the EELAT bit is cleared or a nonvalid EEPROM address is latched. This is to ensure proper programming sequence. Once EEPGM is set, do not read any EEPROM locations; otherwise, the current program cycle will be unsuccessful. When EEPGM is set, the on-board programming sequence will be activated. Advance Information 82 EEPROM For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. EEPROM Functional Description D. The delay time for the EEPGM bit to be cleared in AUTO mode is less than tEEPGM. However, on other MCUs, this delay time may be different. For forward compatibility, software should not make any dependency on this delay time. E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array. EEPROM Erasing The programmed state of an EEPROM bit is logic 0. Erasing changes the state to a logic 1. Only EEPROM bytes in the non-protected blocks and the EENVR register can be erased. Use the following procedure to erase a byte, block or the entire EEPROM array: 1. Configure EERAS1 and EERAS0 for byte, block or bulk erase; set EELAT in EECR.(A) Freescale Semiconductor, Inc... NOTE: If using the AUTO mode, also set the AUTO bit in Step 1. 2. Byte erase: write any data to the desired address.(B) Block erase: write any data to an address within the desired block.(B) Bulk erase: write any data to an address within the array.(B) 3. Set the EEPGM bit.(C) Go to Step 7 if AUTO is set. 4. Wait for a time: tEEBYTE for byte erase; tEEBLOCK for block erase; tEEBULK. for bulk erase. 5. Clear EEPGM bit. 6. Wait for a time, tEEFPV, for the erasing voltage to fall. Go to Step 8. 7. Poll the EEPGM bit until it is cleared by the internal timer.(D) 8. Clear EELAT bits.(E) NOTE: A. Setting the EELAT bit configures the address and data buses to latch data for erasing the array. Only valid EEPROM addresses will be latched. If EELAT is set, other writes to the EECR will be allowed after a valid EEPROM write. 68HC908AZ32A -- Rev 0.0 MOTOROLA EEPROM For More Information On This Product, Go to: www.freescale.com Advance Information 83 Freescale Semiconductor, Inc. EEPROM B. If more than one valid EEPROM write occurs, the last address and data will be latched overriding the previous address and data. Once data is written to the desired address, do not read EEPROM locations other than the written location. (Reading an EEPROM location returns the latched data and causes the read address to be latched). C. The EEPGM bit cannot be set if the EELAT bit is cleared or a nonvalid EEPROM address is latched. This is to ensure proper programming sequence. Once EEPGM is set, do not read any EEPROM locations; otherwise, the current program cycle will be unsuccessful. When EEPGM is set, the on-board programming sequence will be activated. D. The delay time for the EEPGM bit to be cleared in AUTO mode is less than tEEBYTE /tEEBLOCK/tEEBULK. However, on other MCUs, this delay time may be different. For forward compatibility, software should not make any dependency on this delay time. E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array. Freescale Semiconductor, Inc... 5.6 EEPROM Register Descriptions Four I/O registers and three non-volatile registers control program, erase and options of the EEPROM array. Advance Information 84 EEPROM For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. EEPROM EEPROM Register Descriptions 5.6.1 EEPROM Control Register This read/write register controls programming/erasing of the array. Address: $FE1D Bit 7 Read: UNUSED Write: Reset: 0 0 0 = Unimplemented 0 0 0 0 0 6 0 EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 5-2. EEPROM Control Register (EECR) Bit 7-- Unused bit This read/write bit is software programmable but has no functionality. EEOFF -- EEPROM power down This read/write bit disables the EEPROM module for lower power consumption. Any attempts to access the array will give unpredictable results. Reset clears this bit. 1 = Disable EEPROM array 0 = Enable EEPROM array EERAS1 and EERAS0 -- Erase/Program Mode Select Bits These read/write bits set the erase modes. Reset clears these bits. Table 5-3. EEPROM Program/Erase Mode Select EEBPx 0 0 0 0 1 X = don't care EERAS1 0 0 1 1 X EERAS0 0 1 0 1 X MODE Byte Program Byte Erase Block Erase Bulk Erase No Erase/Program 68HC908AZ32A -- Rev 0.0 MOTOROLA EEPROM For More Information On This Product, Go to: www.freescale.com Advance Information 85 Freescale Semiconductor, Inc. EEPROM EELAT -- EEPROM Latch Control This read/write bit latches the address and data buses for programming the EEPROM array. EELAT cannot be cleared if EEPGM is still set. Reset clears this bit. 1 = Buses configured for EEPROM programming or erase operation 0 = Buses configured for normal operation AUTO -- Automatic termination of program/erase cycle When AUTO is set, EEPGM is cleared automatically after the program/erase cycle is terminated by the internal timer. (See note D for EEPROM Programming on page 82, EEPROM Erasing on page 83 and EEPROM Memory Characteristics on page 454) 1 = Automatic clear of EEPGM is enabled 0 = Automatic clear of EEPGM is disabled EEPGM -- EEPROM Program/Erase Enable This read/write bit enables the internal charge pump and applies the programming/erasing voltage to the EEPROM array if the EELAT bit is set and a write to a valid EEPROM location has occurred. Reset clears the EEPGM bit. 1 = EEPROM programming/erasing power switched on 0 = EEPROM programming/erasing power switched off Freescale Semiconductor, Inc... NOTE: Writing logic 0s to both the EELAT and EEPGM bits with a single instruction will clear EEPGM only to allow time for the removal of high voltage. Advance Information 86 EEPROM For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. EEPROM EEPROM Register Descriptions 5.6.2 EEPROM Array Configuration Register The EEPROM array configuration register configures EEPROM security and EEPROM block protection. This read-only register is loaded with the contents of the EEPROM nonvolatile register (EENVR) after a reset. Address: $FE1F Bit 7 6 5 4 3 EEBP3 2 EEBP2 1 EEBP1 Bit 0 EEBP0 Freescale Semiconductor, Inc... Read: UNUSED UNUSED UNUSED EEPRTCT Write: Reset: Contents of EENVR ($FE1C) Figure 5-3. EEPROM Array Configuration Register (EEACR) Bit 7:5 -- Unused Bits These read/write bits are software programmable but have no functionality. EEPRTCT -- EEPROM Protection Bit The EEPRTCT bit is used to enable the security feature in the EEPROM (see 5.5.3 EEPROM Program/Erase Protection). 1 = EEPROM security disabled 0 = EEPROM security enabled This feature is a write-once feature. Once the protection is enabled it may not be disabled. 68HC908AZ32A -- Rev 0.0 MOTOROLA EEPROM For More Information On This Product, Go to: www.freescale.com Advance Information 87 Freescale Semiconductor, Inc. EEPROM EEBP[3:0] -- EEPROM Block Protection Bits These bits prevent blocks of EEPROM array from being programmed or erased. 1 = EEPROM array block is protected 0 = EEPROM array block is unprotected Block Number (EEBPx) EEBP0 EEBP1 EEBP2 EEBP3 Address Range $0800-$087F $0880-$08FF $0900-$097F $0980-$09FF Freescale Semiconductor, Inc... Table 5-4. EEPROM Block Protect and Security Summary Address Range EEBPx EEBP0 = 0 $0800 - $087F EEBP0 = 1 EEBP1 = 0 $0880 - $08EF EEBP1 = 1 EEBP1 = 0 $08F0 - $08FF EEBP1 = 1 EEBP2 = 0 $0900 - $097F EEBP2 = 1 EEBP3 = 0 $0980 - $09FF EEBP3 = 1 EEPRTCT = 1 Byte Programming Available Bulk, Block and Byte Erasing Available Protected Byte Programming Available Bulk, Block and Byte Erasing Available Protected Byte Programming Available Bulk, Block and Byte Erasing Available Protected Byte Programming Available Bulk, Block and Byte Erasing Available Protected Byte Programming Available Bulk, Block and Byte Available Protected Byte Programming Available Only Byte Erasing Available Protected Byte Programming Available Only Byte Erasing Available Protected EEPRTCT = 0 Byte Programming Available Only Byte Erasing Available Protected Byte Programming Available Only Byte Erasing Available Protected Secured (No Programming or Erasing) Advance Information 88 EEPROM For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. EEPROM EEPROM Register Descriptions 5.6.3 EEPROM Nonvolatile Register The contents of this register is loaded into the EEPROM array configuration register (EEACR) after a reset. This register is erased and programmed in the same way as an EEPROM byte. (See EEPROM Control Register on page 85 for individual bit descriptions). Address: $FE1C Bit 7 Read: UNUSED UNUSED UNUSED EEPRTCT Write: Reset: = Unimplemented PV PV = Programmed value or 1 in the erased state. EEBP3 EEBP2 EEBP1 EEBP0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 5-4. EEPROM Nonvolatile Register (EENVR) NOTE: The EENVR will leave the factory programmed with $F0 such that the full array is available and unprotected. 5.6.4 EEPROM Timebase Divider Register The 16-bit EEPROM timebase divider register consists of two 8-bit registers: EEDIVH and EEDIVL. The 11-bit value in this register is used to configure the timebase divider circuit to obtain the 35 s timebase for EEPROM control. These two read/write registers are respectively loaded with the contents of the EEPROM timebase divider on-volatile registers (EEDIVHNVR and EEDIVLNVR) after a reset. 68HC908AZ32A -- Rev 0.0 MOTOROLA EEPROM For More Information On This Product, Go to: www.freescale.com Advance Information 89 Freescale Semiconductor, Inc. EEPROM Address: $FE1A Bit 7 6 0 EEDIVSECD 5 0 4 0 3 0 2 EEDIV10 1 EEDIV9 Bit 0 EEDIV8 Read: Write: Reset: Contents of EEDIVHNVR ($FE10), Bits [6:3] = 0 = Unimplemented Freescale Semiconductor, Inc... Figure 5-5. EEDIV Divider High Register (EEDIVH) Address: $FE1B Bit 7 6 EEDIV6 5 EEDIV5 4 EEDIV4 3 EEDIV3 2 EEDIV2 1 EEDIV1 Bit 0 EEDIV0 Read: EEDIV7 Write: Reset: Contents of EEDIVLNVR ($FE11) Figure 5-6. EEDIV Divider Low Register (EEDIVL) EEDIVSECD -- EEPROM Divider Security Disable This bit enables/disables the security feature of the EEDIV registers. When EEDIV security feature is enabled, the state of the registers EEDIVH and EEDIVL are locked (including EEDIVSECD bit). The EEDIVHNVR and EEDIVLNVR non-volatile memory registers are also protected from being erased/programmed. 1 = EEDIV security feature disabled 0 = EEDIV security feature enabled EEDIV[10:0] -- EEPROM timebase prescaler These prescaler bits store the value of EEDIV which is used as the divisor to derive a timebase of 35s from the selected reference clock source (CGMXCLK or bus block in the CONFIG-2 register) for the EEPROM related internal timer and circuits. EEDIV[10:0] bits are readable at any time. They are writable when EELAT = 0 and EEDIVSECD = 1. Advance Information 90 EEPROM For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. EEPROM EEPROM Register Descriptions The EEDIV value is calculated by the following formula: EEDIV= INT[Reference Frequency(Hz) x 35 x10-6 +0.5] Where the result inside the bracket is rounded down to the nearest integer value For example, if the reference frequency is 4.9152MHz, the EEDIV value is 172 NOTE: Freescale Semiconductor, Inc... Programming/erasing the EEPROM with an improper EEDIV value may result in data lost and reduce endurance of the EEPROM device. 5.6.5 EEPROM Timebase Divider Non-Volatile Register The 16-bit EEPROM timebase divider non-volatile register consists of two 8-bit registers: EEDIVHNVR and EEDIVLNVR. The contents of these two registers are respectively loaded into the EEPROM timebase divider registers, EEDIVH and EEDIVL, after a reset. These two registers are erased and programmed in the same way as an EEPROM byte. Address: $FE10 Bit 7 Read: EEDIVSECD 6 R 5 R 4 R 3 R 2 EEDIV10 1 EEDIV9 Bit 0 EEDIV8 Write: Reset: R Unaffected by reset; $FF when blank = Reserved Figure 5-7. EEPROM Divider Non-Volatile Register High (EEDIVHNVR)) 68HC908AZ32A -- Rev 0.0 MOTOROLA EEPROM For More Information On This Product, Go to: www.freescale.com Advance Information 91 Freescale Semiconductor, Inc. EEPROM Address: $FE11 Bit 7 6 EEDIV6 5 EEDIV5 4 EEDIV4 3 EEDIV3 2 EEDIV2 1 EEDIV1 Bit 0 EEDIV0 Read: EEDIV7 Write: Reset: Unaffected by reset; $FF when blank Freescale Semiconductor, Inc... Figure 5-8. EEPROM Divider Non-Volatile Register Low (EEDIVLNVR) These two registers are protected from erase and program operations if the EEDIVSECD is set to logic 1 in the EEDIVH (see EEPROM Timebase Divider Register) or programmed to a logic 1 in the EEDIVHNVR. NOTE: Once EEDIVSECD in the EEDIVHNVR is programmed to 0 and after a system reset, the EEDIV security feature is permanently enabled because the EEDIVSECD bit in the EEDIVH is always loaded with 0 thereafter. Once this security feature is armed, erase and program mode are disabled for EEDIVHNVR and EEDIVLNVR. Modifications to the EEDIVH and EEDIVL registers are also disabled. Therefore, care should be taken before programming a value into the EEDIVHNVR. 5.7 Low-Power Modes The WAIT and STOP instructions can put the MCU in low powerconsumption standby modes. 5.7.1 Wait Mode The WAIT instruction does not affect the EEPROM. It is possible to start the program or erase sequence on the EEPROM and put the MCU in wait mode. Advance Information 92 EEPROM For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. EEPROM Low-Power Modes 5.7.2 Stop Mode The STOP instruction reduces the EEPROM power consumption to a minimum. The STOP instruction should not be executed while a programming or erasing sequence is in progress. If stop mode is entered while EELAT and EEPGM are set, the programming sequence will be stopped and the programming voltage to the EEPROM array removed. The programming sequence will be restarted after leaving stop mode; access to the EEPROM is only possible after the programming sequence has completed. If stop mode is entered while EELAT and EEPGM is cleared, the programming sequence will be terminated abruptly. In either case, the data integrity of the EEPROM is not guaranteed. Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information EEPROM For More Information On This Product, Go to: www.freescale.com 93 Freescale Semiconductor, Inc. EEPROM Freescale Semiconductor, Inc... Advance Information 94 EEPROM For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 6. Central Processor Unit (CPU) 6.1 Contents 6.2 6.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Freescale Semiconductor, Inc... 6.4 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.4.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 6.4.2 Index register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.4.3 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.4.4 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.4.5 Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . .99 6.2 Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 6.6.1 WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.6.2 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.2 6.2 6.2 CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.2 Introduction This section describes the central processor unit (CPU8). The M68HC08 CPU is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 68HC908AZ32A -- Rev 0.0 MOTOROLA Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Advance Information 95 Freescale Semiconductor, Inc. Central Processor Unit (CPU) 6.3 Features Features of the CPU include the following: * * * * * * * * * * Full upward, object-code compatibility with M68HC05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with X-register manipulation instructions 8.4MHz CPU internal bus frequency 64K byte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Low-power STOP and WAIT Modes Freescale Semiconductor, Inc... 6.4 CPU registers Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map. Advance Information 96 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Central Processor Unit (CPU) CPU registers 7 15 H 15 15 X 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 7 0 V11HINZC CONDITION CODE REGISTER (CCR) Freescale Semiconductor, Inc... CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG Figure 6-1. CPU registers 6.4.1 Accumulator (A) The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 Read: A Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0 Figure 6-2. Accumulator (A) 6.4.2 Index register (H:X) The 16-bit index register allows indexed addressing of a 64K byte memory space. H is the upper byte of the index register and X is the lower byte. H:X is the concatenated 16-bit index register. 68HC908AZ32A -- Rev 0.0 MOTOROLA Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Advance Information 97 Freescale Semiconductor, Inc. Central Processor Unit (CPU) In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. Bit 15 Read: H:X Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X Bit 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X = Indeterminate Freescale Semiconductor, Inc... Figure 6-3. Index register (H:X) The index register can also be used as a temporary data storage location. 6.4.3 Stack pointer (SP) The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Bit 15 Read: SP Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct address (page zero) space. For correct operation, the stack pointer must point only to RAM locations. 68HC908AZ32A -- Rev 0.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MOTOROLA Advance Information 98 Freescale Semiconductor, Inc. Central Processor Unit (CPU) CPU registers 6.4.4 Program counter (PC) The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit 15 Read: PC Write: Reset: Loaded with vector from $FFFE and $FFFF Bit 0 Freescale Semiconductor, Inc... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 6-4. Program counter (PC) 6.4.5 Condition code register (CCR) The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to `1'. The following paragraphs describe the functions of the condition code register. Bit 7 Read: CCR Write: Reset: 6 5 4 3 2 1 Bit 0 V X 1 1 1 1 H X I 1 N X Z X C X X = Indeterminate Figure 6-5. Condition code register (CCR) 68HC908AZ32A -- Rev 0.0 MOTOROLA Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Advance Information 99 Freescale Semiconductor, Inc. Central Processor Unit (CPU) V -- Overflow flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H -- Half-carry flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an ADD or ADC operation. The halfcarry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I -- Interrupt mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled Freescale Semiconductor, Inc... NOTE: To maintain M6805 compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return from interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can only be cleared by the clear interrupt mask software instruction (CLI). Advance Information 100 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Central Processor Unit (CPU) Arithmetic/logic unit (ALU) N -- Negative flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z -- Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C -- Carry/borrow flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions - such as bit test and branch, shift, and rotate - also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 Freescale Semiconductor, Inc... 6.5 Arithmetic/logic unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about CPU architecture. 6.6 Low-power modes The WAIT and STOP instructions put the MCU in low--power consumption standby modes. 68HC908AZ32A -- Rev 0.0 MOTOROLA Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Advance Information 101 Freescale Semiconductor, Inc. Central Processor Unit (CPU) 6.6.1 WAIT mode The WAIT instruction: * clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from WAIT mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock * Freescale Semiconductor, Inc... 6.6.2 STOP mode The STOP instruction: * clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from STOP mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock * After exiting STOP mode, the CPU clock begins running after the oscillator stabilization delay. 6.7 CPU during break interrupts If the break module is enabled, a break interrupt causes the CPU to execute the software interrupt instruction (SWI) at the completion of the current CPU instruction. See Section 11. Break Module. The program counter vectors to $FFFC-$FFFD ($FEFC-$FEFD in monitor mode). A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Advance Information 102 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Central Processor Unit (CPU) Instruction Set Summary 6.8 Instruction Set Summary Table 6-1 provides a summary of the M68HC08 instruction set. Table 6-1. Instruction Set Summary Cycles 2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel Operation Description VH I NZC Freescale Semiconductor, Inc... Add with Carry A (A) + (M) + (C) IMM DIR EXT IX2 - IX1 IX SP1 SP2 IMM DIR EXT - IX2 IX1 IX SP1 SP2 - - - - - - IMM - - - - - - IMM IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2 DIR INH INH - - IX1 IX SP1 DIR INH - - INH IX1 IX SP1 - - - - - - REL A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4 ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff Add without Carry A (A) + (M) Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X SP (SP) + (16 M) H:X (H:X) + (16 M) Logical AND A (A) & (M) Arithmetic Shift Left (Same as LSL) C b7 b0 0 38 dd 48 58 68 ff 78 9E68 ff 37 dd 47 57 67 ff 77 9E67 ff 24 rr Arithmetic Shift Right b7 b0 C Branch if Carry Bit Clear PC (PC) + 2 + rel ? (C) = 0 68HC908AZ32A -- Rev 0.0 MOTOROLA Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Advance Information 103 Operand Address Mode Opcode Effect on CCR Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 6-1. Instruction Set Summary (Continued) Cycles 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 Source Form Operation Description VH I NZC BCLR n, opr Clear Bit n in M Mn 0 DIR (b0) DIR (b1) DIR (b2) - - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL - - - - - - REL - - - - - - REL 11 13 15 17 19 1B 1D 1F 25 27 90 92 28 29 22 24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr Freescale Semiconductor, Inc... BCS rel BEQ rel BGE opr BGT opr BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0 PC (PC) + 2 + rel ? (Z) | (N V) = 0 - - - - - - REL PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2 Bit Test (A) & (M) Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set PC (PC) + 2 + rel ? (Z) | (N V) = 1 - - - - - - REL PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL Advance Information 104 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Operand Address Mode Opcode Effect on CCR Freescale Semiconductor, Inc. Central Processor Unit (CPU) Instruction Set Summary Table 6-1. Instruction Set Summary (Continued) Cycles 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2 3 1 1 1 3 2 4 Source Form BNE rel BPL rel BRA rel Operation Branch if Not Equal Branch if Plus Branch Always Description PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel VH I NZC - - - - - - REL - - - - - - REL - - - - - - REL DIR (b0) DIR (b1) DIR (b2) - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL DIR (b0) DIR (b1) DIR (b2) - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) - - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd Freescale Semiconductor, Inc... BRCLR n,opr,rel Branch if Bit n in M Clear PC (PC) + 3 + rel ? (Mn) = 0 BRN rel Branch Never PC (PC) + 2 BRSET n,opr,rel Branch if Bit n in M Set PC (PC) + 3 + rel ? (Mn) = 1 BSET n,opr Set Bit n in M Mn 1 BSR rel Branch to Subroutine PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (X) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 2 + rel ? (A) - (M) = $00 PC (PC) + 4 + rel ? (A) - (M) = $00 C0 I0 M $00 A $00 X $00 H $00 M $00 M $00 M $00 - - - - - - REL AD rr CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP Clear Carry Bit Clear Interrupt Mask DIR IMM IMM - - - - - - IX1+ IX+ SP1 - - - - - 0 INH - - 0 - - - INH DIR INH INH 0 - - 0 1 - INH IX1 IX SP1 31 41 51 61 71 9E61 98 9A dd rr ii rr ii rr ff rr rr ff rr Clear 3F dd 4F 5F 8C 6F ff 7F 9E6F ff 68HC908AZ32A -- Rev 0.0 MOTOROLA Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Advance Information 105 Operand Address Mode Opcode Effect on CCR Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 6-1. Instruction Set Summary (Continued) Cycles 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5 2 dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 4 1 1 4 3 5 7 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 Source Form CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA Operation Description VH I NZC Compare A with M (A) - (M) IMM DIR EXT - - IX2 IX1 IX SP1 SP2 DIR INH 0 - - 1 INH IX1 IX SP1 IMM - - DIR IMM DIR EXT IX2 -- IX1 IX SP1 SP2 U - - INH A1 B1 C1 D1 E1 F1 9EE1 9ED1 ii dd hh ll ee ff ff ff ee ff Freescale Semiconductor, Inc... Complement (One's Complement) M A X M M M (M) = $FF - (M) (A) = $FF - (M) (X) = $FF - (M) (M) = $FF - (M) (M) = $FF - (M) (M) = $FF - (M) 33 dd 43 53 63 ff 73 9E63 ff 65 75 A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B ii ii+1 dd ii dd hh ll ee ff ff ff ee ff Compare H:X with M (H:X) - (M:M + 1) Compare X with M (X) - (M) Decimal Adjust A (A)10 DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP A (A) - 1 or M (M) - 1 or X (X) - 1 DIR PC (PC) + 3 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 INH PC (PC) + 2 + rel ? (result) 0 - - - - - - INH IX1 PC (PC) + 3 + rel ? (result) 0 IX PC (PC) + 2 + rel ? (result) 0 PC (PC) + 4 + rel ? (result) 0 SP1 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder DIR INH INH - - - IX1 IX SP1 - - - - INH IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2 Decrement 3A dd 4A 5A 6A ff 7A 9E6A ff 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 Divide Exclusive OR M with A A (A M) Advance Information 106 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Operand Address Mode Opcode Effect on CCR Freescale Semiconductor, Inc. Central Processor Unit (CPU) Instruction Set Summary Table 6-1. Instruction Set Summary (Continued) Cycles 4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 5 4 4 4 5 Source Form INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL Operation Description M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1 VH I NZC Increment DIR INH INH --- IX1 IX SP1 DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 0--- IMM DIR 3C dd 4C 5C 6C ff 7C 9E6C ff BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 45 55 AE BE CE DE EE FE 9EEE 9EDE dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff Freescale Semiconductor, Inc... Jump PC Jump Address Jump to Subroutine PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address Load A from M A (M) Load H:X from M H:X (M:M + 1) Load X from M X (M) IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 DIR INH INH - - IX1 IX SP1 DIR INH INH - - 0 IX1 IX SP1 DD DIX+ IMD IX+D Logical Shift Left (Same as ASL) C b7 b0 0 38 dd 48 58 68 ff 78 9E68 ff 34 dd 44 54 64 ff 74 9E64 ff 4E 5E 6E 7E 42 dd dd dd ii dd dd Logical Shift Right 0 b7 b0 C Move (M)Destination (M)Source H:X (H:X) + 1 (IX+D, DIX+) X:A (X) x (A) 0--- Unsigned multiply - 0 - - - 0 INH 68HC908AZ32A -- Rev 0.0 MOTOROLA Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Advance Information 107 Operand Address Mode Opcode Effect on CCR Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 6-1. Instruction Set Summary (Continued) Cycles 4 1 1 4 3 5 1 3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 2 2 2 2 2 2 4 1 1 4 3 5 4 1 1 4 3 5 1 7 4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 Source Form NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP Operation Description VH I NZC M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4]) Negate (Two's Complement) DIR INH - - INH IX1 IX SP1 - - - - - - INH - - - - - - INH IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH DIR INH INH -- IX1 IX SP1 DIR INH - - INH IX1 IX SP1 - - - - - - INH 30 dd 40 50 60 ff 70 9E60 ff 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 86 8A 88 39 dd 49 59 69 ff 79 9E69 ff 36 dd 46 56 66 ff 76 9E66 ff 9C No Operation Nibble Swap A Freescale Semiconductor, Inc... Inclusive OR A and M A (A) | (M) Push A onto Stack Push H onto Stack Push X onto Stack Pull A from Stack Pull H from Stack Pull X from Stack Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1 SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X) Rotate Left through Carry C b7 b0 Rotate Right through Carry b7 b0 C Reset Stack Pointer SP $FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL) RTI Return from Interrupt INH 80 RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP Return from Subroutine - - - - - - INH IMM DIR EXT - - IX2 IX1 IX SP1 SP2 81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 Subtract with Carry A (A) - (M) - (C) Advance Information 108 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Operand Address Mode Opcode Effect on CCR Freescale Semiconductor, Inc. Central Processor Unit (CPU) Instruction Set Summary Table 6-1. Instruction Set Summary (Continued) Cycles 1 2 dd hh ll ee ff ff ff ee ff dd 3 4 4 3 2 4 5 4 1 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 9 2 1 1 Source Form SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP Operation Set Carry Bit Set Interrupt Mask Description C1 I1 VH I NZC - - - - - 1 INH - - 1 - - - INH DIR EXT IX2 0 - - - IX1 IX SP1 SP2 0 - - - DIR - - 0 - - - INH DIR EXT IX2 0 - - - IX1 IX SP1 SP2 IMM DIR EXT IX2 -- IX1 IX SP1 SP2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 Store A in M M (A) Freescale Semiconductor, Inc... Store H:X in M Enable IRQ Pin; Stop Oscillator (M:M + 1) (H:X) I 0; Stop Oscillator Store X in M M (X) Subtract A (A) - (M) SWI Software Interrupt PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR) - - 1 - - - INH 83 TAP TAX TPA Transfer A to CCR Transfer A to X Transfer CCR to A INH - - - - - - INH - - - - - - INH 84 97 85 68HC908AZ32A -- Rev 0.0 MOTOROLA Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Advance Information 109 Operand Address Mode Opcode Effect on CCR Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 6-1. Instruction Set Summary (Continued) Cycles 3 1 1 3 2 4 2 1 2 Source Form TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS Operation Description VH I NZC Test for Negative or Zero (A) - $00 or (X) - $00 or (M) - $00 DIR INH INH 0--- IX1 IX SP1 - - - - - - INH - - - - - - INH - - - - - - INH 3D dd 4D 5D 6D ff 7D 9E6D ff 95 9F 94 Transfer SP to H:X Transfer X to A Transfer H:X to SP H:X (SP) + 1 A (X) (SP) (H:X) - 1 Freescale Semiconductor, Inc... A Accumulatorn C Carry/borrow bitopr CCRCondition code registerPC ddDirect address of operandPCH dd rrDirect address of operand and relative offset of branch instructionPCL DDDirect to direct addressing modeREL DIRDirect addressing moderel DIX+Direct to indexed with post increment addressing moderr ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1 EXTExtended addressing modeSP2 ff Offset byte in indexed, 8-bit offset addressingSP H Half-carry bitU H Index register high byteV hh llHigh and low bytes of operand address in extended addressingX I Interrupt maskZ ii Immediate operand byte& IMDImmediate source to direct destination addressing mode| IMMImmediate addressing mode INHInherent addressing mode( ) IXIndexed, no offset addressing mode-( ) IX+Indexed, no offset, post increment addressing mode# IX+DIndexed with post increment to direct addressing mode IX1Indexed, 8-bit offset addressing mode IX1+Indexed, 8-bit offset, post increment addressing mode? IX2Indexed, 16-bit offset addressing mode: MMemory location N Negative bit-- Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected 6.9 Opcode Map The opcode map is provided in Table 6-2. Advance Information 110 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Operand Address Mode Opcode Effect on CCR Freescale Semiconductor, Inc... Table 6-2. Opcode Map DIR 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F INH Read-Modify-Write INH IX1 SP1 IX IMM DIR EXT IX1 SP1 IX Control INH INH Register/Memory IX2 SP2 MOTOROLA 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 LDX 4 SP2 2 5 STX 4 SP2 2 MSB LSB Bit Manipulation DIR DIR Branch REL 0 1 2 2 4 2 68HC908AZ32A -- Rev 0.0 2 3 1 2 4 1 NEG NEGA DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH 2 3 3 4 2 3 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 4 NEG IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1 5 3 NEG NEG SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX 7 3 RTI BGE INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH 2 SUB IMM 2 CMP IMM 2 SBC IMM 2 CPX IMM 2 AND IMM 2 BIT IMM 2 LDA IMM 2 AIS IMM 2 EOR IMM 2 ADC IMM 2 ORA IMM 2 ADD IMM 3 SUB DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR REL 2 DIR 2 3 LDX LDX IMM 2 DIR 2 3 AIX STX IMM 2 DIR 4 SUB EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT 4 SUB IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2 5 SUB SP2 5 CMP SP2 5 SBC SP2 5 CPX SP2 5 AND SP2 5 BIT SP2 5 LDA SP2 5 STA SP2 5 EOR SP2 5 ADC SP2 5 ORA SP2 5 ADD SP2 3 SUB IX1 3 CMP IX1 3 SBC IX1 3 CPX IX1 3 AND IX1 3 BIT IX1 3 LDA IX1 3 STA IX1 3 EOR IX1 3 ADC IX1 3 ORA IX1 3 ADD IX1 3 JMP IX1 5 JSR IX1 3 LDX IX1 3 STX IX1 4 SUB SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 1 2 SUB IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX 0 Low Byte of Opcode in Hexadecimal 0 SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment High Byte of Opcode in Hexadecimal 5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode Freescale Semiconductor, Inc. Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 MSB 3 DIR LSB 5 0 BRCLR2 1 3 DIR 2 5 3 BRSET3 4 3 DIR 5 5 6 BRCLR3 7 3 DIR 8 5 9 BRSET4 A 3 DIR B C 5 D BRCLR4 E 3 DIR F 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BRA REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL Central Processor Unit (CPU) Opcode Map Advance Information Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions INH IMM DIR EXT DD IX+D 111 Freescale Semiconductor, Inc. Central Processor Unit (CPU) Freescale Semiconductor, Inc... Advance Information 112 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 7. System Integration Module (SIM) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Freescale Semiconductor, Inc... 7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 116 7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . 117 7.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 117 7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 118 7.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 119 7.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . 121 7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 122 7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 122 7.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 123 7.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .123 7.6 Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 7.6.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 7.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 128 7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.8.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 132 68HC908AZ32A -- Rev 0.0 MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Advance Information 113 Freescale Semiconductor, Inc. System Integration Module (SIM) 7.8.2 7.8.3 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 133 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 134 7.2 Introduction This section describes the system integration module (SIM), which supports up to 32 external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 7-1. Figure 7-2 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals - Stop/wait/reset/break entry and recovery - Internal clock control * * Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout Interrupt control: - Acknowledge timing - Arbitration control timing - Vector address generation * CPU enable/disable timing Freescale Semiconductor, Inc... Advance Information 114 68HC908AZ32A -- Rev 0.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. System Integration Module (SIM) Introduction MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) SIM COUNTER COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) Freescale Semiconductor, Inc... /2 CLOCK CONTROL CLOCK GENERATORS INTERNAL CLOCKS RESET PIN LOGIC POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) RESET INTERRUPT CONTROL AND PRIORITY DECODE INTERRUPT SOURCES CPU INTERFACE Figure 7-1. SIM Block Diagram Register Name SIM Break Status Register (SBSR) SIM Reset Status Register (SRSR) SIM Break Flag Control Register (SBFCR) Bit 7 R POR BCFE 6 R PIN R 5 R COP R 4 R ILOP R 3 R ILAD R 2 R 0 R 1 BW LVI R Bit 0 R 0 R R = Reserved Figure 7-2. SIM I/O Register Summary 68HC908AZ32A -- Rev 0.0 MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Advance Information 115 Freescale Semiconductor, Inc. System Integration Module (SIM) Table 7-1. I/O Register Address Summary Register Address SBSR $FE00 SRSR $FE01 SBFCR $FE03 Table 7-2 shows the internal signal names used in this section. Table 7-2. Signal Name Conventions Signal Name CGMXCLK CGMVCLK CGMOUT IAB IDB PORRST IRST R/W Description Buffered Version of OSC1 from Clock Generator Module (CGM) PLL Output PLL-Based or OSC1-Based Clock Output from CGM Module (Bus Clock = CGMOUT Divided by Two) Internal Address Bus Internal Data Bus Signal from the Power-On Reset Module to the SIM Internal Reset Signal Read/Write Signal Freescale Semiconductor, Inc... 7.3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 7-3. This clock can come from either an external oscillator or from the on-chip PLL. (See Section 8. Clock Generator Module (CGM)). 7.3.1 Bus Timing In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four. (See Section 8. Clock Generator Module (CGM)). Advance Information 116 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. System Integration Module (SIM) SIM Bus Clock Control and Generation 7.3.2 Clock Startup from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after 4096 CGMXCLK cycles. The RST pin is driven low by the SIM during this entire period. The bus clocks start upon completion of the timeout. Freescale Semiconductor, Inc... OSC1 CLOCK SELECT CIRCUIT CGMXCLK SIM COUNTER CGMVCLK /2 A CGMOUT B S* *When S = 1, CGMOUT = B /2 BUS CLOCK GENERATORS PLL BCS PTC3 MONITOR MODE USER MODE SIM CGM Figure 7-3. CGM Clock Signals 7.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK cycles. See Stop Mode on page 130. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. 68HC908AZ32A -- Rev 0.0 MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Advance Information 117 Freescale Semiconductor, Inc. System Integration Module (SIM) 7.4 Reset and System Initialization The MCU has these reset sources: * * * * * * Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI) Illegal opcode Illegal address Freescale Semiconductor, Inc... All of these resets produce the vector $FFFE-FFFF ($FEFE-FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see SIM Counter on page 122), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR) (see SIM Registers on page 132). 7.4.1 External Pin Reset Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 7-3 for details. Figure 7-4 shows the relative timing. Table 7-3. PIN Bit Set Timing Reset Type POR/LVI All others Number of Cycles Required to Set PIN 4163 (4096 + 64 + 3) 67 (64 + 3) Advance Information 118 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. System Integration Module (SIM) Reset and System Initialization CGMOUT RST IAB PC VECT H VECT L Figure 7-4. External Reset Timing Freescale Semiconductor, Inc... 7.4.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 75). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR (see Figure 7-6). Note that for LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 7-5. The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. IRST RST RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES CGMXCLK IAB VECTOR HIGH Figure 7-5. Internal Reset Timing 68HC908AZ32A -- Rev 0.0 MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Advance Information 119 Freescale Semiconductor, Inc. System Integration Module (SIM) ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR INTERNAL RESET Figure 7-6. Sources of Internal Reset 7.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. Another sixty-four CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: * * * * * * A POR pulse is generated. The internal reset signal is asserted. The SIM enables CGMOUT. Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow stabilization of the oscillator. The RST pin is driven low during the oscillator stabilization time. The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. Freescale Semiconductor, Inc... Advance Information 120 68HC908AZ32A -- Rev 0.0 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. System Integration Module (SIM) Reset and System Initialization OSC1 PORRST 4096 CYCLES CGMXCLK 32 CYCLES 32 CYCLES CGMOUT Freescale Semiconductor, Inc... RST IAB $FFFE $FFFF Figure 7-7. POR Recovery 7.4.2.2 Computer Operating Properly (COP) Reset The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR) if the COPD bit in the CONFIG-1 register is at logic zero. See Section 13. Computer Operating Properly (COP). 7.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the CONFIG-1 register is logic zero, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. 7.4.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register SRSR) and 68HC908AZ32A -- Rev 0.0 MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Advance Information 121 Freescale Semiconductor, Inc. System Integration Module (SIM) resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. NOTE: Freescale Semiconductor, Inc... Extra care should be exercised if code in this part has been migrated from older HC08 devices since the illegal address reset specification may be different. Also, extra care should be exercised when using this emulation part for development of code to be run in ROM AZ, AB or AS family parts with a smaller memory size since some legal addresses will become illegal addresses on the smaller ROM memory map device and may as a result generate unwanted resets. 7.4.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the VLVII voltage. The LVI bit in the SIM reset status register (SRSR) is set and a chip reset is asserted if the LVIPWRD and LVIRSTD bits in the CONFIG-1 register are at logic zero. The RST pin will be held low until the SIM counts 4096 CGMXCLK cycles after VDD rises above VLVIR. Another sixty-four CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. See Section 14. Low Voltage Inhibit (LVI). 7.5 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of CGMXCLK. 7.5.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM Advance Information 122 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. System Integration Module (SIM) Program Exception Control is initialized, it enables the clock generation module (CGM) to drive the bus clock state machine. 7.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the CONFIG1 register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared. Freescale Semiconductor, Inc... 7.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter. See Stop Mode on page 130 for details. The SIM counter is free-running after all reset states. See Active Resets from Internal Sources on page 119 for counter control and internal reset recovery sequences. 7.6 Program Exception Control Normal, sequential program execution can be changed in three different ways: * Interrupts - Maskable hardware CPU interrupts - Non-maskable software interrupt instruction (SWI) * * Reset Break interrupts 68HC908AZ32A -- Rev 0.0 MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Advance Information 123 Freescale Semiconductor, Inc. System Integration Module (SIM) 7.6.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 7-8 shows interrupt entry timing. Figure 7-10 shows interrupt recovery timing. Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared), see Figure 7-9. MODULE INTERRUPT Freescale Semiconductor, Inc... I BIT IAB DUMMY SP SP - 1 SP - 2 SP - 3 SP - 4 VECT H VECT L START ADDR IDB DUMMY PC - 1[7:0] PC-1[15:8] X A CCR V DATA H V DATA L OPCODE R/W Figure 7-8. Interrupt Entry Advance Information 124 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. System Integration Module (SIM) Program Exception Control FROM RESET YES BREAK INTERRUPT? I BIT SET? NO Freescale Semiconductor, Inc... YES I BIT SET? NO IRQ1 INTERRUPT? NO (AS MANY INTERRUPTS AS EXIST ON CHIP) YES STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI INSTRUCTION? YES NO YES UNSTACK CPU REGISTERS. RTI INSTRUCTION? NO EXECUTE INSTRUCTION. Figure 7-9. Interrupt Processing 68HC908AZ32A -- Rev 0.0 MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Advance Information 125 Freescale Semiconductor, Inc. System Integration Module (SIM) MODULE INTERRUPT I BIT IAB SP - 4 SP - 3 SP - 2 SP - 1 SP PC PC + 1 IDB CCR A X PC - 1 [7:0] PC-1[15:8] OPCODE OPERAND R/W Freescale Semiconductor, Inc... Figure 7-10. Interrupt Recovery Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 7-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M68HC05, M6805 and M146805 Families the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. Advance Information 126 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. System Integration Module (SIM) Program Exception Control CLI LDA #$FF BACKGROUND ROUTINE INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI Freescale Semiconductor, Inc... INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 7-11. Interrupt Recognition Example SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC - 1, as a hardware interrupt does. 7.6.2 Reset All reset sources always have higher priority than interrupts and cannot be arbitrated. 7.6.3 Break Interrupts The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. See Section 11. Break Module. The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt 68HC908AZ32A -- Rev 0.0 MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Advance Information 127 Freescale Semiconductor, Inc. System Integration Module (SIM) subsection of each module to see how each module is affected by the break state. 7.6.4 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a two-step clearing mechanism -- for example, a read of one register followed by the read or write of another -- are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal. Freescale Semiconductor, Inc... 7.7 Low-Power Modes Executing the WAIT or STOP instruction puts the MCU in a low powerconsumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 7.7.1 Wait Mode In wait mode, the CPU clocks are inactive while one set of peripheral clocks continue to run. Figure 7-12 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. Advance Information 128 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. System Integration Module (SIM) Low-Power Modes Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break wait bit, BW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the configuration register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Freescale Semiconductor, Inc... IAB WAIT ADDR WAIT ADDR + 1 SAME SAME IDB PREVIOUS DATA NEXT OPCODE SAME SAME R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 7-12. Wait Mode Entry Timing IAB $6E0B $6E0C $00FF $00FE $00FD $00FC IDB $A6 $A6 $A6 $01 $0B $6E EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt Figure 7-13. Wait Recovery from Interrupt or Break 68HC908AZ32A -- Rev 0.0 MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Advance Information 129 Freescale Semiconductor, Inc. System Integration Module (SIM) 32 Cycles IAB $6E0B 32 Cycles RST VCTH RSTVCTL IDB $A6 $A6 $A6 RST CGMXCLK Freescale Semiconductor, Inc... Figure 7-14. Wait Recovery from Internal Reset 7.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset also causes an exit from stop mode. The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register (CONFIG-1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long startup times from stop mode. NOTE: External crystal applications should use the full stop recovery time by clearing the SSREC bit. The break module is inactive in Stop mode. The STOP instruction does not affect break module register states. The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 7-15 shows stop mode entry timing. Advance Information 130 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. System Integration Module (SIM) Low-Power Modes CPUSTOP IAB STOP ADDR STOP ADDR + 1 SAME SAME IDB PREVIOUS DATA NEXT OPCODE SAME SAME R/W NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. Freescale Semiconductor, Inc... Figure 7-15. Stop Mode Entry Timing STOP RECOVERY PERIOD CGMXCLK INT/BREAK IAB STOP +1 STOP + 2 STOP + 2 SP SP - 1 SP - 2 SP - 3 Figure 7-16. Stop Mode Recovery from Interrupt or Break 68HC908AZ32A -- Rev 0.0 MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Advance Information 131 Freescale Semiconductor, Inc. System Integration Module (SIM) 7.8 SIM Registers The SIM has three memory mapped registers. 7.8.1 SIM Break Status Register The SIM break status register contains a flag to indicate that a break caused an exit from wait mode. Address: $FE00 Bit 7 Read: R Write: Reset: R = Reserved R R R R R See Note 0 NOTE: Writing a logic 0 clears BW 6 5 4 3 2 1 BW R Bit 0 Freescale Semiconductor, Inc... Figure 7-17. SIM Break Status Register (SBSR) BW -- SIM Break Wait This status bit is useful in applications requiring a return to wait mode after exiting from a break interrupt. Clear BW by writing a logic 0 to it. Reset clears BW. 1 = Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt BW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this. Writing zero to the BW bit clears it. ; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE LOBYTE ; EQU EQU 5 6 If not BW, do RTI BRCLR BW,SBSR, RETURN ; See if wait mode was exited by break. ; Advance Information 132 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. System Integration Module (SIM) SIM Registers ; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE LOBYTE ; EQU EQU 5 6 If not BW, do RTI TST BNE DEC DOLO RETURN DEC PULH RTI LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; If RETURNLO is not zero, ; then just decrement low byte. ; Else deal with high byte, too. ; Point to WAIT/STOP opcode. ; Restore H register. Freescale Semiconductor, Inc... 7.8.2 SIM Reset Status Register This register contains six flags that show the source of the last reset. The status register will automatically clear after reading it. A power-on reset sets the POR bit and clears all other bits in the register. Address: $FE01 Bit 7 Read: Write: POR: 1 0 0 0 0 0 0 0 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 0 1 LVI Bit 0 0 = Unimplemented Figure 7-18. SIM Reset Status Register (SRSR) POR -- Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN -- External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR 68HC908AZ32A -- Rev 0.0 MOTOROLA System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Advance Information 133 Freescale Semiconductor, Inc. System Integration Module (SIM) COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD -- Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR LVI -- Low-Voltage Inhibit Reset Bit 1 = Last reset was caused by the LVI circuit 0 = POR or read of SRSR Freescale Semiconductor, Inc... 7.8.3 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Bit 7 Read: Write: Reset: BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R 0 Bit 0 R Figure 7-19. SIM Break Flag Control Register (SBFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break Advance Information 134 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 8. Clock Generator Module (CGM) 8.1 Contents 8.2 8.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Freescale Semiconductor, Inc... 8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .139 8.4.2.1 Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.4.2.2 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . 141 8.4.2.3 Manual and Automatic PLL Bandwidth Modes . . . . . . . 141 8.4.2.4 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . .143 8.4.2.5 Special Programming Exceptions . . . . . . . . . . . . . . . . . 145 8.4.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . 145 8.4.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . 146 8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . 147 8.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . 147 8.5.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . 147 8.5.4 Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.5.5 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . 148 8.5.6 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . 148 8.5.7 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . . 148 8.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 148 8.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 8.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 8.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . 151 8.6.3 PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . . 153 8.7 8.8 68HC908AZ32A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Advance Information 135 Freescale Semiconductor, Inc. Clock Generator Module (CGM) 8.8.1 8.8.2 8.9 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 156 8.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .156 8.10.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . . 156 8.10.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . 158 8.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 159 8.10.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . 159 Freescale Semiconductor, Inc... 8.2 Introduction The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, from which the system clocks are derived. CGMOUT is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency generator designed for use with 1-MHz to 16-MHz crystals or ceramic resonators. The PLL can generate an 8-MHz bus frequency without using high frequency crystals. 8.3 Features Features of the CGM include: * * * * * Phase-Locked Loop with Output Frequency in Integer Multiples of the Crystal Reference Programmable Hardware Voltage-Controlled Oscillator (VCO) for Low-Jitter Operation Automatic Bandwidth Control Mode for Low-Jitter Operation Automatic Frequency Lock Detector CPU Interrupt on Entry or Exit from Locked Condition Advance Information 136 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) Functional Description 8.4 Functional Description The CGM consists of three major submodules: * * * Crystal oscillator circuit -- The crystal oscillator circuit generates the constant crystal frequency clock, CGMXCLK. Phase-locked loop (PLL) -- The PLL generates the programmable VCO frequency clock CGMVCLK. Base clock selector circuit -- This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The system clocks are derived from CGMOUT. Freescale Semiconductor, Inc... Figure 8-1 shows the structure of the CGM. 8.4.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal enables the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock. CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float. 68HC908AZ32A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Advance Information 137 Freescale Semiconductor, Inc. Clock Generator Module (CGM) OSC1 CLOCK SELECT CIRCUIT CGMRDV CGMRCLK BCS A CGMXCLK /2 CGMOUT B S* *When S = 1, CGMOUT = B PTC3 VDDA CGMXFC VSS VRS7-VRS4 MONITOR MODE USER MODE PHASE DETECTOR LOOP FILTER PLL ANALOG VOLTAGE CONTROLLED OSCILLATOR Freescale Semiconductor, Inc... LOCK DETECTOR BANDWIDTH CONTROL INTERRUPT CONTROL CGMINT LOCK AUTO ACQ PLLIE PLLF MUL7-MUL4 CGMVDV FREQUENCY DIVIDER CGMVCLK Figure 8-1. CGM Block Diagram Advance Information 138 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) Functional Description Register Name Read: PLL Control Register (PCTL) Write: Reset: Read: PLL Bandwidth Control Register Write: (PBWC) Reset: Read: PLL Programming Register (PPG) Write: Reset: Bit 7 PLLIE 0 6 PLLF 0 LOCK 0 5 PLLON 1 4 BCS 0 3 1 1 0 0 2 1 1 0 0 1 1 1 0 0 Bit 0 1 1 0 0 AUTO 0 ACQ 0 XLD 0 Freescale Semiconductor, Inc... MUL7 0 MUL6 1 MUL5 1 MUL4 0 VRS7 0 VRS6 1 VRS5 1 VRS4 0 = Unimplemented Figure 8-2. I/O Register Summary Table 8-1. I/O Register Address Summary Register Address PCTL $001C PBWC $001D PPG $001E 8.4.2 Phase-Locked Loop Circuit (PLL) The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually. 8.4.2.1 Circuits The PLL consists of these circuits: * * * * * 68HC908AZ32A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Voltage-controlled oscillator (VCO) Modulo VCO frequency divider Phase detector Loop filter Lock detector Advance Information 139 Freescale Semiconductor, Inc. Clock Generator Module (CGM) The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fCGMVRS. Modulating the voltage on the CGMXFC pin changes the frequency within this range. By design, fCGMVRS is equal to the nominal center-ofrange frequency, fNOM, (4.9152 MHz) times a linear factor L or (L)fNOM. CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency, fCGMRCLK, and is fed to the PLL through a buffer. The buffer output is the final reference clock, CGMRDV, running at a frequency fCGMRDV = fCGMRCLK. The VCO's output clock, CGMVCLK, running at a frequency fCGMVCLK, is fed back through a programmable modulo divider. The modulo divider reduces the VCO clock by a factor, N. The divider's output is the VCO feedback clock, CGMVDV, running at a frequency fCGMVDV = fCGMVCLK/N. See 8.4.2.4 Programming the PLL for more information. The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter then slightly alters the dc voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, as described in Acquisition and Tracking Modes on page 141. The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL. The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, fCGMRDV. The circuit determines the mode of the PLL and the lock condition based on this comparison. Freescale Semiconductor, Inc... Advance Information 140 68HC908AZ32A -- Rev 0.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) Functional Description 8.4.2.2 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: * Acquisition mode -- In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. See PLL Bandwidth Control Register on page 151. Tracking mode -- In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected as the base clock source. See Base Clock Selector Circuit on page 145. The PLL is automatically in tracking mode when it's not in acquisition mode or when the ACQ bit is set. Freescale Semiconductor, Inc... * 8.4.2.3 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See PLL Bandwidth Control Register on page 151. If PLL CPU interrupt requests are enabled, the software can wait for a PLL CPU interrupt request and then check the LOCK bit. If CPU interrupts are disabled, software can poll the LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set, the VCO clock is safe to use as the source for the base clock. See Base Clock Selector Circuit on page 145. If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. See Interrupts on page 155. 68HC908AZ32A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Advance Information 141 Freescale Semiconductor, Inc. Clock Generator Module (CGM) These conditions apply when the PLL is in automatic bandwidth control mode: * The ACQ bit (See 8.6.2 PLL Bandwidth Control Register.) is a read-only indicator of the mode of the filter. See Acquisition and Tracking Modes on page 141. The ACQ bit is set when the VCO frequency is within a certain tolerance, trk, and is cleared when the VCO frequency is out of a certain tolerance, unt. See Electrical Specifications on page 444. The LOCK bit is a read-only indicator of the locked state of the PLL. The LOCK bit is set when the VCO frequency is within a certain tolerance, Lock, and is cleared when the VCO frequency is out of a certain tolerance, unl. See Electrical Specifications on page 444. CPU interrupts can occur if enabled (PLLIE = 1) when the PLL's lock condition changes, toggling the LOCK bit. See PLL Control Register on page 149. * Freescale Semiconductor, Inc... * * * The PLL also can operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below fbusmax and require fast startup. The following conditions apply when in manual mode: * ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. Before entering tracking mode (ACQ = 1), software must wait a given time, tacq (see Electrical Specifications on page 444), after turning on the PLL by setting PLLON in the PLL control register (PCTL). Software must wait a given time, tal, after entering tracking mode before selecting the PLL as the clock source to CGMOUT (BCS = 1). The LOCK bit is disabled. 68HC908AZ32A -- Rev 0.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com MOTOROLA * * * Advance Information 142 Freescale Semiconductor, Inc. Clock Generator Module (CGM) Functional Description * CPU interrupts from the CGM are disabled. 8.4.2.4 Programming the PLL Use this 9-step procedure to program the PLL. The table below lists the variables used and their meaning (Please also reference Figure 8-1 on page 138). Table 8-2. Variable Definitions Variable Definition Desired Bus Clock Frequency Desired VCO Clock Frequency Chosen Reference Crystal Frequency Calculated VCO Clock Frequency Calculated Bus Clock Frequency Nominal VCO Center Frequency Shifted VCO Center Frequency Freescale Semiconductor, Inc... fBUSDES fVCLKDES fCGMRCLK fCGMVCLK fBUS fNOM fCGMVRS 1. Choose the desired bus frequency, fBUSDES. Example: fBUSDES = 8 MHz 2. Calculate the desired VCO frequency, fVCLKDES. fVCLKDES = 4 x fBUSDES Example: fVCLKDES = 4 x 8 MHz = 32 MHz 3. Using a reference frequency, fRCLK, equal to the crystal frequency, calculate the VCO frequency multiplier, N. Round the result to the nearest integer. f VCLKDES N = ------------------------fCGMRCLK 32 MHz Example: N = ------------------- = 8 4 MHz 4. Calculate the VCO frequency, fCGMVCLK. 68HC908AZ32A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Advance Information 143 Freescale Semiconductor, Inc. Clock Generator Module (CGM) f CGMVCLK = N x f CGMRCLK Example: fCGMVCLK = 8 x 4 MHz = 32 MHz 5. Calculate the bus frequency, fBUS, and compare fBUS with fBUSDES. f CGMVCLK f BUS = ----------------------4 32 MHz Example: f BUS = ------------------- = 8 MHz 4 6. If the calculated fbus is not within the tolerance limits of your application, select another fBUSDES or another fRCLK. 7. Using the value 4.9152 MHz for fNOM, calculate the VCO linear range multiplier, L. The linear range multiplier controls the frequency range of the PLL. f CGMVCLK L = round ----------------------- f NOM - 32 MHz ------------------------------- = 7 4.9152 MHz Freescale Semiconductor, Inc... Example: L = 8. Calculate the VCO center-of-range frequency, fCGMVRS. The center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL. fCGMVRS = L x fNOM Example: fCGMVRS = 7 x 4.9152 MHz = 34.4 MHz NOTE: f NOM For proper operation, f CGMVRS - f CGMVCLK ---------------. 2 Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. 9. Program the PLL registers accordingly: Advance Information 144 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) Functional Description a. In the upper four bits of the PLL programming register (PPG), program the binary equivalent of N. b. In the lower four bits of the PLL programming register (PPG), program the binary equivalent of L. 8.4.2.5 Special Programming Exceptions The programming method described in Programming the PLL on page 143, does not account for two possible exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these exceptions: * * A 0 value for N is interpreted the same as a value of 1. A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See Base Clock Selector Circuit on page 145. Freescale Semiconductor, Inc... 8.4.3 Base Clock Selector Circuit This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK). The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock. 68HC908AZ32A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Advance Information 145 Freescale Semiconductor, Inc. Clock Generator Module (CGM) 8.4.4 CGM External Connections In its typical configuration, the CGM requires seven external components. Five of these are for the crystal oscillator and two are for the PLL. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 8-3. Figure 8-3 shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: * * * * * Crystal, X1 Fixed capacitor, C1 Tuning capacitor, C2 (can also be a fixed capacitor) Feedback resistor, RB Series resistor, RS (optional) Freescale Semiconductor, Inc... The series resistor (RS) may not be required for all ranges of operation, especially with high-frequency crystals. Refer to the crystal manufacturer's data for more information. Figure 8-3 also shows the external components for the PLL: * * Bypass capacitor, CBYP Filter capacitor, CF Routing should be done with great care to minimize signal cross talk and noise. (See Acquisition/Lock Time Specifications on page 156 for routing information and more information on the filter capacitor's value and its effects on PLL performance). Advance Information 146 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) I/O Signals SIMOSCEN CGMXCLK OSC1 OSC2 CGMXFC VDDA VSS RS* RB VDD CF CBYP X1 Freescale Semiconductor, Inc... C1 C2 *RS can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer's data. Figure 8-3. CGM External Connections 8.5 I/O Signals The following paragraphs describe the CGM input/output (I/O) signals. 8.5.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 8.5.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. 8.5.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is connected to this pin. NOTE: To prevent noise problems, CF should be placed as close to the CGMXFC pin as possible with minimum routing distances and no routing of other signals across the CF connection. Advance Information Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 147 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) 8.5.4 Analog Power Pin (VDDA) VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage potential as the VDD pin. NOTE: Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 8.5.5 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal enables the oscillator and PLL. Freescale Semiconductor, Inc... 8.5.6 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fCGMXCLK) and comes directly from the crystal oscillator circuit. Figure 8-3 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at startup. 8.5.7 CGM Base Clock Output (CGMOUT) CGMOUT is the clock output of the CGM. This signal is used to generate the MCU clocks. CGMOUT is a 50% duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two. 8.5.8 CGM CPU Interrupt (CGMINT) CGMINT is the CPU interrupt signal generated by the PLL lock detector. 8.6 CGM Registers Three registers control and monitor operation of the CGM: Advance Information 148 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) CGM Registers * * * PLL control register (PCTL) PLL bandwidth control register (PBWC) PLL programming register (PPG) 8.6.1 PLL Control Register The PLL control register contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit. Address: $001C Bit 7 Read: PLLIE Write: Reset: 0 0 1 0 1 1 1 1 6 PLLF PLLON BCS 5 4 3 1 2 1 1 1 Bit 0 1 Freescale Semiconductor, Inc... = Unimplemented Figure 8-4. PLL Control Register (PCTL) PLLIE -- PLL Interrupt Enable Bit This read/write bit enables the PLL to generate a CPU interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit. 1 = PLL CPU interrupt requests enabled 0 = PLL CPU interrupt requests disabled 68HC908AZ32A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Advance Information 149 Freescale Semiconductor, Inc. Clock Generator Module (CGM) PLLF -- PLL Flag Bit This read-only bit is set whenever the LOCK bit toggles. PLLF generates a CPU interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit. 1 = Change in lock condition 0 = No change in lock condition Freescale Semiconductor, Inc... NOTE: Do not inadvertently clear the PLLF bit. Be aware that any read or readmodify-write operation on the PLL control register clears the PLLF bit. PLLON -- PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). See Base Clock Selector Circuit on page 145. Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on 0 = PLL off BCS -- Base Clock Select Bit This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. See Base Clock Selector Circuit on page 145. Reset and the STOP instruction clear the BCS bit. 1 = CGMVCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT NOTE: PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off Advance Information 150 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) CGM Registers (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. See Base Clock Selector Circuit on page 145. PCTL3-PCTL0 -- Unimplemented These bits provide no function and always read as logic 1s. 8.6.2 PLL Bandwidth Control Register The PLL bandwidth control register: * * * * Selects automatic or manual (software-controlled) bandwidth control mode Indicates when the PLL is locked In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode In manual operation, forces the PLL into acquisition or tracking mode $001D Bit 7 Read: AUTO Write: Reset: 0 0 0 0 0 0 0 0 6 LOCK ACQ XLD 5 4 3 0 2 0 1 0 Bit 0 0 Freescale Semiconductor, Inc... Address: = Unimplemented Figure 8-5. PLL Bandwidth Control Register (PBWC) 68HC908AZ32A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Advance Information 151 Freescale Semiconductor, Inc. Clock Generator Module (CGM) AUTO -- Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK -- Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked ACQ -- Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode XLD -- Crystal Loss Detect Bit When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit can indicate whether the crystal reference frequency is active or not. 1 = Crystal reference not active 0 = Crystal reference active Freescale Semiconductor, Inc... Advance Information 152 68HC908AZ32A -- Rev 0.0 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) CGM Registers To check the status of the crystal reference, do the following: 1. Write a logic 1 to XLD. 2. Wait N x 4 cycles. N is the VCO frequency multiplier. 3. Read XLD. The crystal loss detect function works only when the BCS bit is set, selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD always reads as logic 0. Bits 3-0 -- Reserved for Test These bits enable test functions not available in user mode. To ensure software portability from development systems to user applications, software should write 0s to bits 3-0 when writing to PBWC. Freescale Semiconductor, Inc... 8.6.3 PLL Programming Register The PLL programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the VCO. Address: $001E Bit 7 Read: MUL7 Write: Reset: 0 1 1 0 0 1 1 0 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 6 5 4 3 2 1 Bit 0 Figure 8-6. PLL Programming Register (PPG) MUL7-MUL4 -- Multiplier Select Bits These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier, N. (See Circuits on page 139 and Programming the PLL on page 143). A value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. Reset initializes these bits to $6 to give a default multiply value of 6. 68HC908AZ32A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Advance Information 153 Freescale Semiconductor, Inc. Clock Generator Module (CGM) Table 8-3. VCO Frequency Multiplier (N) Selection MUL7:MUL6:MUL5:MUL4 0000 0001 0010 0011 VCO Frequency Multiplier (N) 1 1 2 3 Freescale Semiconductor, Inc... 1101 1110 1111 13 14 15 NOTE: The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1). VRS7-VRS4 -- VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L, which controls the hardware center-of-range frequency, fVRS. (See Circuits on page 139, Programming the PLL on page 143, and PLL Control Register on page 149.) VRS7-VRS4 cannot be written when the PLLON bit in the PLL control register (PCTL) is set. See Special Programming Exceptions on page 145. A value of $0 in the VCO range select bits disables the PLL and clears the BCS bit in the PCTL. (See Base Clock Selector Circuit on page 145 and Special Programming Exceptions on page 145 for more information.) Reset initializes the bits to $6 to give a default range multiply value of 6. NOTE: The VCO range select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1) and prevents selection of the VCO clock as the source of the base clock (BCS = 1) if the VCO range select bits are all clear. The VCO range select bits must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock. Advance Information 154 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) Interrupts 8.7 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupt requests from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether CPU interrupt requests are enabled or not. When the AUTO bit is clear, CPU interrupt requests from the PLL are disabled and PLLF reads as logic 0. Software should read the LOCK bit after a PLL CPU interrupt request to see if the request was due to an entry into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency sensitive, CPU interrupt requests should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations. Freescale Semiconductor, Inc... NOTE: Software can select the CGMVCLK divided by two as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit. 8.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 8.8.1 Wait Mode The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive applications can disengage the PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL. 68HC908AZ32A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Advance Information 155 Freescale Semiconductor, Inc. Clock Generator Module (CGM) 8.8.2 Stop Mode The STOP instruction disables the CGM and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If CGMOUT is being driven by CGMVCLK and a STOP instruction is executed; the PLL will clear the BCS bit in the PLL control register, causing CGMOUT to be driven by CGMXCLK. When the MCU recovers from STOP, the crystal clock divided by two drives CGMOUT and BCS remains clear. Freescale Semiconductor, Inc... 8.9 CGM During Break Interrupts The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See Section 11. Break Module. To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. 8.10 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 8.10.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the Advance Information 156 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) Acquisition/Lock Time Specifications Freescale Semiconductor, Inc... step input or when the output settles to the desired value plus or minus a percent of the frequency change. Therefore, the reaction time is constant in this definition, regardless of the size of the step input. For example, consider a system with a 5% acquisition time tolerance. If a command instructs the system to change from 0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz 50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a -100 kHz noise hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz 5 kHz. Five kHz = 5% of the 100-kHz step input. Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock time varies according to the original error in the output. Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. The discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical PLL. Therefore, the definitions for acquisition and lock times for this module are: * Acquisition time, tacq, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, trk. Acquisition time is based on an initial frequency error, (fdes - forig)/fdes, of not more than 100%. In automatic bandwidth control mode (see Manual and Automatic PLL Bandwidth Modes on page 141), acquisition time expires when the ACQ bit becomes set in the PLL bandwidth control register (PBWC). Lock time, tLock, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance, Lock. Lock time is based on an initial frequency error, (fdes - forig)/fdes, of not more than 100%. In automatic bandwidth control mode, lock time * 68HC908AZ32A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Advance Information 157 Freescale Semiconductor, Inc. Clock Generator Module (CGM) expires when the LOCK bit becomes set in the PLL bandwidth control register (PBWC). (See Manual and Automatic PLL Bandwidth Modes on page 141). Obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases. 8.10.2 Parametric Influences on Reaction Time Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. The most critical parameter which affects the reaction times of the PLL is the reference frequency, fCGMRDV (please reference Figure 8-1 on page 138). This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections. This parameter is also under user control via the choice of crystal frequency fCGMXCLK. Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by adding or subtracting charge from this capacitor. Therefore, the rate at which the voltage changes for a given frequency error (thus a change in charge) is proportional to the capacitor size. The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may not be able to adjust the voltage in a reasonable time. See Choosing a Filter Capacitor on page 159. Also important is the operating voltage potential applied to VDDA. The power supply potential alters the characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL. Advance Information 158 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGM) Acquisition/Lock Time Specifications Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 8.10.3 Choosing a Filter Capacitor As described in Parametric Influences on Reaction Time on page 158, the external filter capacitor, CF, is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. The value of the capacitor must, therefore, be chosen with supply potential and reference frequency in mind. For proper operation, the external filter capacitor must be chosen according to this equation: V DDA C F = C fact ------------------ fCGMRDV For acceptable values of Cfact, (see Electrical Specifications on page 444). For the value of VDDA, choose the voltage potential at which the MCU is operating. If the power supply is variable, choose a value near the middle of the range of possible supply values. This equation does not always yield a commonly available capacitor size, so round to the nearest available size. If the value is between two different sizes, choose the higher value for better stability. Choosing the lower size may seem attractive for acquisition time improvement, but the PLL may become unstable. Also, always choose a capacitor with a tight tolerance (20% or better) and low dissipation. Freescale Semiconductor, Inc... 8.10.4 Reaction Time Calculation The actual acquisition and lock times can be calculated using the equations below. These equations yield nominal values under the following conditions: 68HC908AZ32A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Advance Information 159 Freescale Semiconductor, Inc. Clock Generator Module (CGM) * * * * Correct selection of filter capacitor, CF (see Choosing a Filter Capacitor on page 159). Room temperature operation Negligible external leakage on CGMXFC Negligible noise Freescale Semiconductor, Inc... The K factor in the equations is derived from internal PLL parameters. Kacq is the K factor when the PLL is configured in acquisition mode, and Ktrk is the K factor when the PLL is configured in tracking mode. (See Acquisition and Tracking Modes on page 141). V DDA 8 t acq = ------------------- ------------ f CGMRDV K ACQ V DDA 4 t al = ------------------- ----------- f CGMRDV K TRK t Lock = t ACQ + t AL Note the inverse proportionality between the lock time and the reference frequency. In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (See Manual and Automatic PLL Bandwidth Modes on page 141). A certain number of clock cycles, nACQ, is required to ascertain that the PLL is within the tracking mode entry tolerance, TRK, before exiting acquisition mode. A certain number of clock cycles, nTRK, is required to ascertain that the PLL is within the lock mode entry tolerance, Lock. Therefore, the acquisition time, tACQ, is an integer multiple of nACQ/fCGMRDV, and the acquisition to lock time, tAL, is an integer multiple of nTRK/fCGMRDV. Also, since the average frequency over the entire measurement period must be within the specified tolerance, the total time usually is longer than tLock as calculated above. Advance Information 160 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) Acquisition/Lock Time Specifications In manual mode, it is usually necessary to wait considerably longer than tLock before selecting the PLL clock (see Base Clock Selector Circuit on page 145), because the factors described in Parametric Influences on Reaction Time on page 158, may slow the lock time considerably. When defining a limit in software for the maximum lock time, the value must allow for variation due to all of the factors mentioned in this section, especially due to the CF capacitor and application specific influences. The calculated lock time is only an indication and it is the customer's responsibility to allow enough of a guard band for their application. Prior to finalizing any software and while determining the maximum lock time, take into account all device to device differences. Typically, applications set the maximum lock time as an order of magnitude higher than the measured value. This is considered sufficient for all such device to device variation. Motorola recommends measuring the lock time of the application system by utilizing dedicated software, running in FLASH, EEPROM or RAM. This should toggle a port pin when the PLL is first configured and switched on, then again when it goes from acquisition to lock mode and finally again when the PLL lock bit is set. The resultant waveform can be captured on an oscilloscope and used to determine the typical lock time for the microcontroller and the associated external application circuit. e.g. tLOCK tACQ Init. low Freescale Semiconductor, Inc... tAL Signal on port pin tTRKComplete and Lock Set tACQComplete PLL Configured and switched on NOTE: The filter capacitor should be fully discharged prior to making any measurements. Advance Information Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 161 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Clock Generator Module (CGM) Freescale Semiconductor, Inc... Advance Information 162 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 9. Configuration Register (CONFIG-1) 9.1 Contents 9.2 9.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Freescale Semiconductor, Inc... 9.2 Introduction This section describes the configuration register (CONFIG-1), which contains bits that configure these options: * * * * * * Resets caused by the LVI module Power to the LVI module LVI enabled during stop mode Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) Computer operating properly module (COP) STOP instruction enable/disable. 9.3 Functional Description The configuration register is a write-once register. Out of reset, the configuration register will read the default value. Once the register is written, further writes will have no effect until a reset occurs. NOTE: If the LVI module and the LVI reset signal are enabled, a reset occurs when VDD falls to a voltage, LVITRIPF, and remains at or below that level 68HC908AZ32A -- Rev 0.0 MOTOROLA Configuration Register (CONFIG-1) For More Information On This Product, Go to: www.freescale.com Advance Information 163 Freescale Semiconductor, Inc. Configuration Register (CONFIG-1) for at least nine consecutive CPU cycles. Once an LVI reset occurs, the MCU remains in reset until VDD rises to a voltage, LVITRIPR. Address: $001F Bit 7 Read: LVISTOP Write: Reset: 0 R 1 = Reserved 1 1 0 0 0 0 R LVIRST LVIPWR SSREC COPRS STOP COPD 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 9-1. Configuration Register (CONFIG-1) LVISTOP -- LVI Stop Mode Enable Bit LVISTOP enables the LVI module in stop mode. (See Section 14. Low Voltage Inhibit (LVI)). 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode NOTE: To have the LVI enabled in stop mode, the LVIPWR must be at a logic 1 and the LVISTOP bit must be at a logic 1. Take note that by enabling the LVI in stop mode, the stop IDD current will be higher. LVIRST -- LVI Reset Enable Bit LVIRST enables the reset signal from the LVI module. (See Section 14. Low Voltage Inhibit (LVI)). 1 = LVI module resets enabled 0 = LVI module resets disabled Advance Information 164 Configuration Register (CONFIG-1) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Configuration Register (CONFIG-1) Functional Description LVIPWR -- LVI Power Enable Bit LVIPWR enables the LVI module. (See Section 14. Low Voltage Inhibit (LVI)). 1 = LVI module power enabled 0 = LVI module power disabled SSREC -- Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. (See Stop Mode on page 130). 1 = Stop mode recovery after 32 CGMXCLK cycles 0 = Stop mode recovery after 4096 CGMXCLK cycles Freescale Semiconductor, Inc... NOTE: If using an external crystal oscillator, do not set the SSREC bit. COPRS -- COP Rate Select Bit COPRS enables the shorter COP timeout period. (See Section 13. Computer Operating Properly (COP)). 1 = COP timeout period is 213 - 24 CGMXCLK cycles 0 = COP timeout period is 218 - 24 CGMXCLK cycles STOP -- STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP Disable Bit COPD disables the COP module. (See Section 13. Computer Operating Properly (COP)). 1 = COP module disabled 0 = COP module enabled Extra care should be exercised when using this emulation part for development of code to be run in ROM AZ or AB parts that the options selected by setting the CONFIG-1 register match exactly the options selected on any ROM code request submitted. The enable/disable logic is not necessarily identical in all parts of the AZ and AB families. If in doubt, check with your local field applications representative. 68HC908AZ32A -- Rev 0.0 MOTOROLA Configuration Register (CONFIG-1) For More Information On This Product, Go to: www.freescale.com Advance Information 165 Freescale Semiconductor, Inc. Configuration Register (CONFIG-1) Freescale Semiconductor, Inc... Advance Information 166 Configuration Register (CONFIG-1) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 10. Configuration Register (CONFIG-2) 10.1 Contents 10.2 10.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Freescale Semiconductor, Inc... 10.2 Introduction This section describes the configuration register (CONFIG-2). This register contains bits that configure these options: * * EEPROM Reference Clock Source EEPROM Read Protection 10.3 Functional Description The configuration register is a write-once register. Out of reset, the configuration register will read the default. Once the register is written, further writes will have no effect until a reset occurs. Address: $FE09 Bit 7 Read: Write: Reset: EEDIV CLK 0 6 R 0 5 R 0 4 EEMONSEC 3 AZ32A 2 R 1 R 0 Bit 0 R 0 R 1 R 0 = Reserved 1 Figure 10-1. Configuration Register (CONFIG-2) 68HC908AZ32A -- Rev 0.0 MOTOROLA Configuration Register (CONFIG-2) For More Information On This Product, Go to: www.freescale.com Advance Information 167 Freescale Semiconductor, Inc. Configuration Register (CONFIG-2) EEDIVCLK -- EEPROM Timebase Divider Clock select bit This bit selects the reference clock source for the EEPROM-1 and EEPROM-2 timebase divider modules. 1 = EExDIV clock input is driven by internal bus clock 0 = EExDIV clock input is driven by CGMXCLK EEMONSEC -- EEPROM Read Protection in Monitor Mode Bit When EEMONSEC is set the entire EEPROM array cannot be accessed in monitor mode unless a valid security code is entered. 1 = EEPROM read protection in monitor mode enabled 0 = EEPROM read protection in monitor mode disabled AZ32A -- Device indicator This read-only bit is used to indicate that the MC68HC908AZ32A is an `A' suffix version HC08 rather than a non-'A'. 1 = `A' version 0 = Non-'A' version Freescale Semiconductor, Inc... Advance Information 168 68HC908AZ32A -- Rev 0.0 Configuration Register (CONFIG-2) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 11. Break Module 11.1 Contents 11.2 11.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Freescale Semiconductor, Inc... 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .171 11.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 171 11.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 172 11.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 172 11.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 11.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 11.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . 173 11.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .174 11.2 Introduction The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 11.3 Features * * * * 68HC908AZ32A -- Rev 0.0 MOTOROLA Break Module For More Information On This Product, Go to: www.freescale.com Accessible I/O Registers during Break Interrupts CPU-Generated Break Interrupts Software-Generated Break Interrupts COP Disabling during Break Interrupts Advance Information 169 Freescale Semiconductor, Inc. Break Module 11.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: * * A CPU-generated address (the address in the program counter) matches the contents of the break address registers. Software writes a logic 1 to the BRKA bit in the break status and control register. Freescale Semiconductor, Inc... When a CPU-generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 11-1 shows the structure of the break module. IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW BREAK IAB[7:0] Figure 11-1. Break Module Block Diagram Advance Information 170 Break Module For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Break Module Functional Description Register Name Read: Break Address Register High Write: (BRKH) Reset: Read: Break Address Register Low Write: (BRKL) Reset: Read: Break Status and Control Register Write: (BSCR) Reset: Bit 7 Bit 15 0 6 14 0 5 13 0 4 12 0 3 11 0 2 10 0 1 9 0 Bit 0 Bit 8 0 Bit 7 0 6 0 5 0 0 0 4 0 0 0 R = Reserved 3 0 0 0 2 0 0 0 1 0 0 0 Bit 0 0 0 0 Freescale Semiconductor, Inc... BRKE 0 BRKA 0 = Unimplemented Figure 11-2. I/O Register Summary Table 11-1. I/O Register Address Summary Register Address BRKH $FE0C BRKL $FE0D BSCR $FE0B 11.4.1 Flag Protection During Break Interrupts The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. 11.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: * * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode) 68HC908AZ32A -- Rev 0.0 MOTOROLA Break Module For More Information On This Product, Go to: www.freescale.com Advance Information 171 Freescale Semiconductor, Inc. Break Module The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. 11.4.3 TIM During Break Interrupts A break interrupt stops the timer counter. Freescale Semiconductor, Inc... 11.4.4 COP During Break Interrupts The COP is disabled during a break interrupt when VHi is present on the RST pin. 11.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 11.5.1 Wait Mode If enabled, the break module is active in wait mode. The SIM break wait bit (BW) in the SIM break status register indicates whether wait was exited by a break interrupt. If so, the user can modify the return address on the stack by subtracting one from it. (See SIM Break Status Register on page 132). 11.5.2 Stop Mode The break module is inactive in stop mode. The STOP instruction does not affect break module register states. Advance Information 172 Break Module For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Break Module Break Module Registers 11.6 Break Module Registers These registers control and monitor operation of the break module: * * * Break address register high (BRKH) Break address register low (BRKL) Break status and control register (BSCR) 11.6.1 Break Status and Control Register The break status and control register contains break module enable and status bits. Address: $FE0B Bit 7 Read: BRKE Write: Reset: 0 0 0 0 0 0 0 0 BRKA 6 5 0 4 0 3 0 2 0 1 0 Bit 0 0 Freescale Semiconductor, Inc... = Unimplemented Figure 11-3. Break Status and Control Register (BSCR) BRKE -- Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match BRKA -- Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = (When read) Break address match 0 = (When read) No break address match 68HC908AZ32A -- Rev 0.0 MOTOROLA Break Module For More Information On This Product, Go to: www.freescale.com Advance Information 173 Freescale Semiconductor, Inc. Break Module 11.6.2 Break Address Registers The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Register: Address: BRKH $FE0C Bit 7 Read: Bit 15 Write: Reset: Read: Bit 7 Write: Reset: 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8 BRKL $FE0D 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 11-4. Break Address Registers (BRKH and BRKL) Advance Information 174 Break Module For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 12. Monitor ROM (MON) 12.1 Contents 12.2 12.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Freescale Semiconductor, Inc... 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 12.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 12.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 12.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 12.4.4 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 12.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 12.4.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 12.4.7 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 12.2 Introduction This section describes the monitor ROM (MON). The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. 12.3 Features Features of the monitor ROM include: * * * Normal User-Mode Pin Functionality One Pin Dedicated to Serial Communication between Monitor ROM and Host Computer Standard Mark/Space Non-Return-to-Zero (NRZ) Communication with Host Computer 68HC908AZ32A -- Rev 0.0 MOTOROLA Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Advance Information 175 Freescale Semiconductor, Inc. Monitor ROM (MON) * * * * Up to 28.8 kBaud Communication with Host Computer Execution of Code in RAM or FLASH FLASH Security FLASH Programming 12.4 Functional Description Monitor ROM receives and executes commands from a host computer. Figure 12-1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. While simple monitor commands can access any memory address, the 68HC908AZ32A has a FLASH security feature to prevent external viewing of the contents of FLASH. Proper procedures must be followed to verify FLASH content. Access to the FLASH is denied to unauthorized users of customer specified software (see Security on page 185). In monitor mode, the MCU can execute host-computer code in RAM while all MCU pins except PTA0 retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. Freescale Semiconductor, Inc... Advance Information 176 68HC908AZ32A -- Rev 0.0 Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description VDD 68HC08 10 k RST 0.1 F VHI 1 K IRQ 9.1V Freescale Semiconductor, Inc... CGMXFC 1 10 F + 3 4 10 F + MC145407 20 + 18 17 + 2 19 10 F VDD 20 pF 20 pF X1 4.9152 MHz 10 F * 10 M OSC2 VDDA 0.1 F VDDA/VDDAREF VSSA VSS 5 6 16 15 0.1 F VDD VDD 0.022 F OSC1 DB-25 2 3 7 VDD 1 2 6 4 MC74HC125 14 3 5 VDD 10 k A (SEE NOTE.) VDD 10 k PTA0 PTC3 VDD 10 k PTC0 PTC1 7 NOTE: Position A -- Bus clock = CGMXCLK / 4 or CGMVCLK / 4 Position B -- Bus clock = CGMXCLK / 2 B * = Refer to Table 12-9 for correct value. Figure 12-1. Monitor Mode Circuit 68HC908AZ32A -- Rev 0.0 MOTOROLA Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Advance Information 177 Freescale Semiconductor, Inc. Monitor ROM (MON) 12.4.1 Entering Monitor Mode Table 12-1 shows the pin conditions for entering monitor mode. Table 12-1. Mode Selection PTC0 Pin PTC1 Pin PTA0 Pin PTC3 Pin IRQ1 Pin Bus Frequency Mode CGMOUT Freescale Semiconductor, Inc... VHI(1) 1 0 1 1 Monitor CGMXCLK CGMVCLK ---------------------------- or ---------------------------2 2 CGMOUT ------------------------2 CGMOUT ------------------------2 VHI(1) 1 0 1 0 Monitor CGMXCLK 1. For VHI, 5.0 Volt DC Electrical Characteristics on page 446, and Maximum Ratings on page 444. Enter monitor mode by either * * Executing a software interrupt instruction (SWI) or Applying a logic 0 and then a logic 1 to the RST pin. Once out of reset, the MCU waits for the host to send eight security bytes (see Security on page 185). After the security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host computer, indicating that it is ready to receive a command. Monitor mode uses alternate vectors for reset, SWI and break interrupt. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. The COP module is disabled in monitor mode as long as VHI (see 5.0 Volt DC Electrical Characteristics on page 446), is applied to either the IRQ1 pin or the RESET pin. (See Section 7. System Integration Module (SIM) for more information on modes of operation). NOTE: Holding the PTC3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator. The CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. 68HC908AZ32A -- Rev 0.0 Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com MOTOROLA Advance Information 178 Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description Table 12-2 is a summary of the differences between user mode and monitor mode. Table 12-2. Mode Differences Functions Modes COP User Monitor Enabled Disabled(1) Reset Vector High $FFFE $FEFE Reset Vector Low $FFFF $FEFF Break Vector High $FFFC $FEFC Break Vector Low $FFFD $FEFD SWI Vector High $FFFC $FEFC SWI Vector Low $FFFD $FEFD Freescale Semiconductor, Inc... 1. If the high voltage (VHI) is removed from the IRQ and/or RESET pin while in monitor mode, the SIM asserts its COP enable output. The COP is enabled or disabled by the COPD bit in the configuration register. (see 5.0 Volt DC Electrical Characteristics on page 446). 12.4.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 12-2 and Figure 12-3.) The data transmit and receive rate can be anywhere up to 28.8 kBaud. Transmit and receive baud rates must be identical. START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT Figure 12-2. Monitor Data Format $A5 START BIT START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT STOP BIT NEXT START BIT BREAK BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 NEXT START BIT Figure 12-3. Sample Monitor Waveforms 68HC908AZ32A -- Rev 0.0 MOTOROLA Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Advance Information 179 Freescale Semiconductor, Inc. Monitor ROM (MON) 12.4.3 Echoing As shown in Figure 12-4, the monitor ROM immediately echoes each received byte back to the PTA0 pin for error checking. Any result of a command appears after the echo of the last byte of the command. Freescale Semiconductor, Inc... SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA ECHO RESULT Figure 12-4. Read Transaction 12.4.4 Break Signal A start bit followed by nine low bits is a break signal. (See Figure 12-5). When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal. MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Figure 12-5. Break Transaction Advance Information 180 Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description 12.4.5 Commands The monitor ROM uses these commands: * * * * * * READ, read memory WRITE, write memory IREAD, indexed read IWRITE, indexed write READSP, read stack pointer RUN, run user program Freescale Semiconductor, Inc... A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 12-3. READ (Read Memory) Command Description Operand Data Returned Opcode Read byte from memory Specifies 2-byte address in high byte:low byte order Returns contents of specified address $4A Command Sequence SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA ECHO RESULT 68HC908AZ32A -- Rev 0.0 MOTOROLA Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Advance Information 181 Freescale Semiconductor, Inc. Monitor ROM (MON) Table 12-4. WRITE (Write Memory) Command Description Operand Data Returned Opcode Write byte to memory Specifies 2-byte address in high byte:low byte order; low byte followed by data byte None $49 Command Sequence SENT TO MONITOR Freescale Semiconductor, Inc... WRITE WRITE ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA DATA ECHO Table 12-5. IREAD (Indexed Read) Command Description Operand Data Returned Opcode Read next 2 bytes in memory from last address accessed Specifies 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence SENT TO MONITOR IREAD IREAD DATA DATA ECHO RESULT Advance Information 182 Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description Table 12-6. IWRITE (Indexed Write) Command Description Operand Data Returned Opcode Write to last address accessed + 1 Specifies single data byte None $19 Command Sequence SENT TO MONITOR IWRITE IWRITE DATA DATA Freescale Semiconductor, Inc... ECHO Table 12-7. READSP (Read Stack Pointer) Command Description Operand Data Returned Opcode Reads stack pointer None Returns stack pointer in high byte:low byte order $0C Command Sequence SENT TO MONITOR READSP READSP SP HIGH SP LOW ECHO RESULT 68HC908AZ32A -- Rev 0.0 MOTOROLA Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Advance Information 183 Freescale Semiconductor, Inc. Monitor ROM (MON) Table 12-8. RUN (Run User Program) Command Description Operand Data Returned Opcode Executes RTI instruction None None $28 Command Sequence SENT TO MONITOR RUN RUN Freescale Semiconductor, Inc... ECHO 12.4.6 Baud Rate The 68HC908AZ32A features a monitor mode which is optimised to operate with either a 4.9152 MHz crystal clock source (or multiples of 4.9152 MHz) or a 4 MHz crystal (or multiples of 4 MHz). This supports designs which use the MSCAN module, which is generally clocked from a 4 MHz, 8 MHz or 16 MHZ internal reference clock. The table below outlines the available baud rates for a range of crystals and how they can match to a PC baud rate. Table 12-9 68HC908AZ32A Monitor Baud Rate Selection Baud rate Clock freq 32kHz 1MHz 2MHz 4MHz 4.194MHz PTC3=0 57.97 1811.59 3623.19 7246.37 7597.83 PTC3=1 28.98 905.80 1811.59 3623.19 3798.91 Closest PC baud PC PTC3=0 57.6 1800 3600 7200 7680 PTC3=1 28.8 900 1800 3600 3840 Error % PTC3=0 0.64 0.64 0.64 0.64 1.08 PTC3=1 0.63 0.64 0.64 0.64 1.08 Advance Information 184 Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description Table 12-9 68HC908AZ32A Monitor Baud Rate Selection Baud rate 4.9152MHz 8MHz 16MHz 8904.35 14492.72 28985.51 4452.17 7246.37 14492.75 Closest PC baud PC 8861 14400 28800 4430 7200 14400 Error % 0.49 0.64 0.64 0.50 0.64 0.64 Care should be taken when setting the baud rate since incorrect baud rate setting can result in communications failure. Freescale Semiconductor, Inc... 12.4.7 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6-$FFFD. Locations $FFF6-$FFFD contain userdefined data. NOTE: Do not leave locations $FFF6-$FFFD blank. For security reasons, program locations $FFF6-$FFFD even if they are not used for vectors. If FLASH is unprogrammed, the eight security byte values to be sent are $FF, the unprogrammed state of FLASH. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PA0. 68HC908AZ32A -- Rev 0.0 MOTOROLA Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Advance Information 185 Freescale Semiconductor, Inc. Monitor ROM (MON) VDD 4096 + 32 CGMXCLK CYCLES RST 24 BUS CYCLES (MINIMUM) Command 1 Byte 2 Echo Byte 8 Echo 2 Break 4 1 Command Echo Byte 1 Byte 2 Byte 8 1 FROM HOST PA0 1 Byte 1 Echo FROM MCU 4 Freescale Semiconductor, Inc... NOTE: 1 = Echo delay (2 bit times) 2 = Data return delay (2 bit times) 4 = Wait 1 bit time before sending next byte. Figure 12-6. Monitor Mode Entry Timing If the received bytes match those at locations $FFF6-$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. After the host bypasses security, any reset other than a power-on reset requires the host to send another eight bytes. If the reset was not a power-on reset, the security remains bypassed regardless of the data that the host sends. If the received bytes do not match the data at locations $FFF6-$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading FLASH locations returns undefined data, and trying to execute code from FLASH causes an illegal address reset. After the host fails to bypass security, any reset other than a power-on reset causes an endless loop of illegal address resets. After receiving the eight security bytes from the host, the MCU transmits a break character signalling that it is ready to receive a command. NOTE: The MCU does not transmit a break character until after the host sends the eight security bytes. Advance Information 186 Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 13. Computer Operating Properly (COP) 13.1 Contents 13.2 13.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Freescale Semiconductor, Inc... 13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.4.7 COPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.4.8 COPRS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.5 13.6 13.7 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 13.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.9 COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 192 13.2 Introduction The COP module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by periodically clearing the COP counter. 68HC908AZ32A -- Rev 0.0 MOTOROLA Computer Operating Properly (COP) For More Information On This Product, Go to: www.freescale.com Advance Information 187 Freescale Semiconductor, Inc. Computer Operating Properly (COP) 13.3 Functional Description The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 213 - 24 or 218 - 24 CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the CONFIG-1 register. When COPRS = 0, a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 4-12 of the SIM counter. Freescale Semiconductor, Inc... NOTE: Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status register (RSR). In monitor mode, the COP is disabled if the RST pin or the IRQ pin is held at VHi. During the break state, VHi on the RST pin disables the COP. NOTE: Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. Advance Information 188 Computer Operating Properly (COP) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Computer Operating Properly (COP) I/O Signals 13.4 I/O Signals The following paragraphs describe the signals shown in Figure 13-1. 12-BIT COP PRESCALER CGMXCLK CLEAR ALL STAGES CLEAR STAGES 4-12 Freescale Semiconductor, Inc... STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH COPCTL WRITE RESET RESET STATUS REGISTER 6-BIT COP COUNTER COPD FROM CONFIG-1 RESET COPCTL WRITE CLEAR COP COUNTER COPRS FROM CONFIG-1 Figure 13-1. COP Block Diagram 13.4.1 CGMXCLK CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency. 13.4.2 STOP Instruction The STOP instruction clears the COP prescaler. 68HC908AZ32A -- Rev 0.0 MOTOROLA Computer Operating Properly (COP) For More Information On This Product, Go to: www.freescale.com Advance Information 189 Freescale Semiconductor, Inc. Computer Operating Properly (COP) 13.4.3 COPCTL Write Writing any value to the COP control register (COPCTL) (see COP Control Register on page 191), clears the COP counter and clears stages 12 through 4 of the COP prescaler. Reading the COP control register returns the reset vector. 13.4.4 Power-On Reset The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up. Freescale Semiconductor, Inc... 13.4.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. 13.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 13.4.7 COPD The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. (See Section 9. Configuration Register (CONFIG-1)). 13.4.8 COPRS The COPRS signal reflects the state of the COP rate select bit. (COPRS) in the configuration register. (See Section 9. Configuration Register (CONFIG-1)). Advance Information 190 Computer Operating Properly (COP) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Computer Operating Properly (COP) COP Control Register 13.5 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Address: $FFFF Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Low Byte of Reset Vector Clear COP Counter Unaffected by Reset Figure 13-2. COP Control Register (COPCTL) 13.6 Interrupts The COP does not generate CPU interrupt requests. 13.7 Monitor Mode The COP is disabled in monitor mode when VHi is present on the IRQ1 pin or on the RST pin. 13.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 13.8.1 Wait Mode The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 68HC908AZ32A -- Rev 0.0 MOTOROLA Computer Operating Properly (COP) For More Information On This Product, Go to: www.freescale.com Advance Information 191 Freescale Semiconductor, Inc. Computer Operating Properly (COP) 13.8.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the configuration register (CONFIG-1) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. Freescale Semiconductor, Inc... 13.9 COP Module During Break Interrupts The COP is disabled during a break interrupt when VHi is present on the RST pin. Advance Information 192 Computer Operating Properly (COP) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 14. Low Voltage Inhibit (LVI) 14.1 Contents 14.2 14.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Freescale Semiconductor, Inc... 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.4.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.4.3 False Reset Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.5 14.6 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.2 Introduction This section describes the low-voltage inhibit module (LVI47, Version A), which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls to the LVI trip voltage. 14.3 Features Features of the LVI module include: * * * Programmable LVI Reset Programmable Power Consumption Digital Filtering of VDD Pin Level Advance Information Low Voltage Inhibit (LVI) For More Information On This Product, Go to: www.freescale.com 193 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Low Voltage Inhibit (LVI) NOTE: If a low voltage interrupt (LVI) occurs during programming of EEPROM or Flash memory, then adequate programming time may not have been allowed to ensure the integrity and retention of the data. It is the responsibility of the user to ensure that in the event of an LVI any addresses being programmed receive specification programming conditions. 14.4 Functional Description Figure 14-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWR, enables the LVI to monitor VDD voltage. The LVI reset bit, LVIRST, enables the LVI module to generate a reset when VDD falls below a voltage, LVITRIPF, and remains at or below that level for nine or more consecutive CPU cycles. Note that short VDD spikes may not trip the LVI. It is the user's responsibility to ensure a clean VDD signal within the specified operating voltage range if normal microcontroller operation is to be guaranteed. LVISTOP, enables the LVI module during stop mode. This will ensure when the STOP instruction is implemented, the LVI will continue to monitor the voltage level on VDD. LVIPWR, LVISTOP, and LVIRST are in the configuration register, CONFIG-1 (see Section 9. Configuration Register (CONFIG-1)). Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, LVITRIPR. VDD must be above LVITRIPR for only one CPU cycle to bring the MCU out of reset (see Forced Reset Operation on page 196). The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices. Freescale Semiconductor, Inc... Advance Information 194 68HC908AZ32A -- Rev 0.0 Low Voltage Inhibit (LVI) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Low Voltage Inhibit (LVI) Functional Description VDD LVIPWR FROM CONFIG-1 CPU CLOCK LOW VDD DETECTOR VDD > LVITRIP = 0 VDD < LVITRIP = 1 Stop Mode Filter Bypass ANLGTRIP LVISTOP FROM CONFIG-1 LVIOUT VDD DIGITAL FILTER FROM CONFIG-1 LVIRST LVI RESET Freescale Semiconductor, Inc... Figure 14-1. LVI Module Block Diagram 68HC908AZ32A -- Rev 0.0 MOTOROLA Low Voltage Inhibit (LVI) For More Information On This Product, Go to: www.freescale.com Advance Information 195 Freescale Semiconductor, Inc. Low Voltage Inhibit (LVI) Figure 14-2. LVI I/O Register Summary Addr. $FE0F Register Name Bit 7 6 5 4 3 2 1 Bit 0 LVI Status Register (LVISR) LVIOUT = Unimplemented Freescale Semiconductor, Inc... 14.4.1 Polled LVI Operation In applications that can operate at VDD levels below the LVITRIPF level, software can monitor VDD by polling the LVIOUT bit. In the configuration register, the LVIPWR bit must be at logic 1 to enable the LVI module, and the LVIRST bit must be at logic 0 to disable LVI resets. 14.4.2 Forced Reset Operation In applications that require VDD to remain above the LVITRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls to the LVITRIPF level and remains at or below that level for nine or more consecutive CPU cycles. In the configuration register, the LVIPWR and LVIRST bits must be at logic 1 to enable the LVI module and to enable LVI resets. 14.4.3 False Reset Protection The VDD pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI module to reset the MCU,VDD must remain at or below the LVITRIPF level for nine or more consecutive CPU cycles. VDD must be above LVITRIPR for only one CPU cycle to bring the MCU out of reset. Advance Information 196 Low Voltage Inhibit (LVI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Low Voltage Inhibit (LVI) LVI Status Register 14.5 LVI Status Register The LVI status register flags VDD voltages below the LVITRIPF level. Address: $FE0F Bit 7 Read: LVIOUT Write: Reset: 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 Freescale Semiconductor, Inc... = Unimplemented Figure 14-3. LVI Status Register (LVISR) LVIOUT -- LVI Output Bit This read-only flag becomes set when the VDD voltage falls below the LVITRIPF voltage for 32 to 40 CGMXCLK cycles. (See Table 14-1). Reset clears the LVIOUT bit. Table 14-1. LVIOUT Bit Indication VDD At Level: VDD > LVITRIPR VDD < LVITRIPF VDD < LVITRIPF VDD < LVITRIPF LVITRIPF < VDD < LVITRIPR For Number of CGMXCLK Cycles: Any < 32 CGMXCLK Cycles Between 32 and 40 CGMXCLK Cycles > 40 CGMXCLK Cycles Any LVIOUT 0 0 0 or 1 1 Previous Value 14.6 LVI Interrupts The LVI module does not generate interrupt requests. 68HC908AZ32A -- Rev 0.0 MOTOROLA Low Voltage Inhibit (LVI) For More Information On This Product, Go to: www.freescale.com Advance Information 197 Freescale Semiconductor, Inc. Low Voltage Inhibit (LVI) 14.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 14.7.1 Wait Mode With the LVIPWR bit in the configuration register programmed to logic 1, the LVI module is active after a WAIT instruction. With the LVIRST bit in the configuration register programmed to logic 1, the LVI module can generate a reset and bring the MCU out of wait mode. Freescale Semiconductor, Inc... 14.7.2 Stop Mode With the LVISTOP and LVIPWR bits in the configuration register programmed to a logic 1, the LVI module will be active after a STOP instruction. Because CPU clocks are disabled during stop mode, the LVI trip must bypass the digital filter to generate a reset and bring the MCU out of stop. With the LVIPWR bit in the configuration register programmed to logic 1 and the LVISTOP bit at a logic 0, the LVI module will be inactive after a STOP instruction. Note that the LVI feature is intended to provide the safe shutdown of the microcontroller and thus protection of related circuitry prior to any application VDD voltage collapsing completely to an unsafe level. It is not intended that users operate the microcontroller at lower than specified operating voltage VDD. Advance Information 198 Low Voltage Inhibit (LVI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 15. External Interrupt Module (IRQ1) 15.1 Contents 15.2 15.3 15.4 15.5 15.6 15.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .204 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 204 Freescale Semiconductor, Inc... 15.2 Introduction This section describes the nonmaskable external interrupt (IRQ) input. 15.3 Features Features include: * * * * Dedicated External Interrupt Pin (IRQ1) Hysteresis Buffer Programmable Edge-Only or Edge- and Level-Interrupt Sensitivity Automatic Interrupt Acknowledge 15.4 Functional Description A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 15-1 shows the structure of the IRQ module. 68HC908AZ32A -- Rev 0.0 MOTOROLA External Interrupt Module (IRQ1) For More Information On This Product, Go to: www.freescale.com Advance Information 199 Freescale Semiconductor, Inc. External Interrupt Module (IRQ1) Interrupt signals on the IRQ1 pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: * Vector fetch -- A vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch. Software clear -- Software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (ISCR). Writing a logic 1 to the ACK bit clears the IRQ latch. Reset -- A reset automatically clears both interrupt latches. * Freescale Semiconductor, Inc... * ACK INTERNAL ADDRESS BUS TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER VDD D IRQ1 CLR Q SYNCHRONIZER IRQF CK IRQ LATCH IMASK IRQ INTERRUPT REQUEST MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC Figure 15-1. IRQ Block Diagram The external interrupt pin is falling-edge triggered and is softwareconfigurable to be both falling-edge and low-level triggered. The MODE bit in the ISCR controls the triggering sensitivity of the IRQ1 pin. When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software clear, or reset occurs. Advance Information 200 External Interrupt Module (IRQ1) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. External Interrupt Module (IRQ1) Functional Description Table 15-1. IRQ I/O Register Summary Addr. $001A Register Name Read: IRQ Status/Control Register (ISCR) Write: R R R R R ACK Bit 7 0 6 0 5 0 4 0 3 IRQF 2 0 IMASK MODE 1 Bit 0 R = Reserved Freescale Semiconductor, Inc... When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of the following occur: * * Vector fetch or software clear Return of the interrupt pin to logic 1 The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the ISCR masks all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the corresponding IMASK bit is clear. NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. (See Figure 15-2). 68HC908AZ32A -- Rev 0.0 MOTOROLA External Interrupt Module (IRQ1) For More Information On This Product, Go to: www.freescale.com Advance Information 201 Freescale Semiconductor, Inc. External Interrupt Module (IRQ1) FROM RESET YES I BIT SET? NO INTERRUPT? NO YES Freescale Semiconductor, Inc... STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI INSTRUCTION? NO YES RTI INSTRUCTION? NO YES UNSTACK CPU REGISTERS. EXECUTE INSTRUCTION. Figure 15-2. IRQ Interrupt Flowchart 15.5 IRQ Pin A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. Advance Information 202 External Interrupt Module (IRQ1) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. External Interrupt Module (IRQ1) IRQ Pin If the MODE bit is set, the IRQ1 pin is both falling-edge sensitive and low-level sensitive. With MODE set, both of the following actions must occur to clear the IRQ latch: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK bit in the interrupt status and control register (ISCR). The ACK bit is useful in applications that poll the IRQ1 pin and require software to clear the IRQ latch. Writing to the ACK bit can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ1 pin. A falling edge on IRQ that occurs after writing to the ACK bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. Return of the IRQ1 pin to logic 1 -- As long as the IRQ1 pin is at logic 0, the IRQ1 latch remains set. Freescale Semiconductor, Inc... * The vector fetch or software clear and the return of the IRQ1 pin to logic 1 can occur in any order. The interrupt request remains pending as long as the IRQ1 pin is at logic 0. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ1 pin is falling-edge sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the ISCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ1 pin. NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. 68HC908AZ32A -- Rev 0.0 MOTOROLA External Interrupt Module (IRQ1) For More Information On This Product, Go to: www.freescale.com Advance Information 203 Freescale Semiconductor, Inc. External Interrupt Module (IRQ1) 15.6 IRQ Module During Break Interrupts The system integration module (SIM) controls whether the IRQ interrupt latch can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latches during the break state. (See SIM Break Flag Control Register on page 134 To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch. Freescale Semiconductor, Inc... 15.7 IRQ Status and Control Register The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR has these functions: * * * * Address: Shows the state of the IRQ interrupt flag Clears the IRQ interrupt latch Masks IRQ interrupt request Controls triggering sensitivity of the IRQ1 interrupt pin $001A Bit 7 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 IRQF R 0 2 0 IMASK MODE 0 ACK 0 0 1 Bit 0 Read: Write: Reset: 0 R 0 R Figure 15-3. IRQ Status and Control Register (ISCR) Advance Information 204 External Interrupt Module (IRQ1) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. External Interrupt Module (IRQ1) IRQ Status and Control Register IRQF -- IRQ Flag Bit This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK -- IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as logic 0. Reset clears ACK. IMASK -- IRQ Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE -- IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE. 1 = IRQ1 interrupt requests on falling edges and low levels 0 = IRQ1 interrupt requests on falling edges only Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information External Interrupt Module (IRQ1) For More Information On This Product, Go to: www.freescale.com 205 Freescale Semiconductor, Inc. External Interrupt Module (IRQ1) Freescale Semiconductor, Inc... Advance Information 206 External Interrupt Module (IRQ1) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 16. Serial Communications Interface (SCI) 16.1 Contents 16.2 16.3 16.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Freescale Semiconductor, Inc... 16.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 16.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.5.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.5.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.5.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 16.5.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . . 217 16.5.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 217 16.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 16.5.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 16.5.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 16.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 16.5.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 16.5.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 16.5.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16.5.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 16.5.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 16.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 228 16.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 16.8.1 PTE0/SCTxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . 228 16.8.2 PTE1/SCRxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . 229 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 207 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 16.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 16.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 16.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 16.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 16.9.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 16.9.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Freescale Semiconductor, Inc... 16.2 Introduction The SCI allows asynchronous communications with peripheral devices and other MCUs. 16.3 Features The SCI module's features include: * * * * * * * * Full Duplex Operation Standard Mark/Space Non-Return-to-Zero (NRZ) Format 32 Programmable Baud Rates Programmable 8-Bit or 9-Bit Character Length Separately Enabled Transmitter and Receiver Separate Receiver and Transmitter CPU Interrupt Requests Programmable Transmitter Output Polarity Two Receiver Wakeup Methods: - Idle Line Wakeup - Address Mark Wakeup * Interrupt-Driven Operation with Eight Interrupt Flags: - Transmitter Empty - Transmission Complete - Receiver Full Advance Information 208 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Pin Name Conventions - Idle Receiver Input - Receiver Overrun - Noise Error - Framing Error - Parity Error * * * Receiver Framing Error Detection Hardware Parity Checking 1/16 Bit-Time Noise Detection Freescale Semiconductor, Inc... 16.4 Pin Name Conventions The generic names of the SCI input/output (I/O) pins are: * * RxD (receive data) TxD (transmit data) SCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output reflects the name of the shared port pin. Table 16-1 shows the full names and the generic names of the SCI I/O pins.The generic pin names appear in the text of this section. Table 16-1. Pin Name Conventions Generic Pin Names Full Pin Names RxD PTE1/SCRxD TxD PTE0/SCTxD 16.5 Functional Description Figure 16-1 shows the structure of the SCI module. The SCI allows fullduplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 209 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) INTERNAL BUS TRANSMITTER INTERRUPT CONTROL SCI DATA REGISTER RECEIVE SHIFT REGISTER SCI DATA REGISTER RECEIVER INTERRUPT CONTROL ERROR INTERRUPT CONTROL TRANSMIT SHIFT REGISTER TXINV RxD TxD SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCTE TC SCRF IDLE OR NF FE PE LOOPS LOOPS WAKEUP CONTROL RECEIVE CONTROL BKF RPF BAUD RATE GENERATOR FLAG CONTROL M WAKE ILTY CGMXCLK PEN PTY DATA SELECTION CONTROL ENSCI R8 T8 Freescale Semiconductor, Inc... ORIE NEIE FEIE PEIE TRANSMIT CONTROL ENSCI /4 PRESCALER / 16 Figure 16-1. SCI Module Block Diagram Advance Information 210 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description Register Name SCI Control Register 1 (SCC1) SCI Control Register 2 (SCC2) SCI Control Register 3 (SCC3) Freescale Semiconductor, Inc... SCI Status Register 1 (SCS1) SCI Status Register 2 (SCS2) SCI Data Register (SCDR) SCI Baud Rate Register (SCBR) Bit 7 Read: LOOPS Write: Reset: 0 Read: SCTIE Write: Reset: 0 Read: R8 Write: Reset: U Read: SCTE Write: Reset: 1 Read: 0 Write: Reset: 0 Read: R7 Write: T7 Reset: Read: 0 Write: Reset: 0 6 ENSCI 0 TCIE 0 T8 U TC 1 0 0 R6 T6 0 0 5 TXINV 0 SCRIE 0 R 0 SCRF 0 0 0 R5 T5 SCP1 0 4 M 0 ILIE 0 R 0 IDLE 0 0 3 WAKE 0 TE 0 ORIE 0 OR 0 0 2 ILTY 0 RE 0 NEIE 0 NF 0 0 0 R2 T2 SCR2 0 R = Reserved 1 PEN 0 RWU 0 FEIE 0 FE 0 BKF 0 R1 T1 SCR1 0 Bit 0 PTY 0 SBK 0 PEIE 0 PE 0 RPF 0 R0 T0 SCR0 0 0 0 R4 R3 T4 T3 Unaffected by Reset SCP0 0 U = Unaffected R 0 = Unimplemented Figure 16-2. SCI I/O Register Summary Table 16-2. SCI I/O Register Address Summary Register Address SCC1 $0013 SCC2 $0014 SCC3 $0015 SCS1 $0016 SCS2 $0017 SCDR $0018 SCBR $0019 16.5.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 16-3. 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 211 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 8-BIT DATA FORMAT (BIT M IN SCC1 CLEAR) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 PARITY OR DATA BIT BIT 7 STOP BIT NEXT START BIT 9-BIT DATA FORMAT (BIT M IN SCC1 SET) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 PARITY OR DATA BIT BIT 7 BIT 8 STOP BIT NEXT START BIT Figure 16-3. SCI Data Formats Freescale Semiconductor, Inc... 16.5.2 Transmitter Figure 16-4 shows the structure of the SCI transmitter. 16.5.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). 16.5.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the TxD pin. The SCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1). 2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in SCI control register 2 (SCC2). 3. Clear the SCI transmitter empty bit (SCTE) by first reading SCI status register 1 (SCS1) and then writing to the SCDR. 4. Repeat step 3 for each subsequent transmission. At the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. After the Advance Information 212 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description preamble shifts out, control logic transfers the SCDR data into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU interrupt request. When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port E pins. Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 213 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) INTERNAL BUS /4 CGMXCLK SCP1 SCP0 SCR1 SCR2 SCR0 TRANSMITTER CPU INTERRUPT REQUEST PRESCALER BAUD DIVIDER / 16 SCI DATA REGISTER H 8 7 6 5 4 3 2 1 0 START L STOP 11-BIT TRANSMIT SHIFT REGISTER TxD Freescale Semiconductor, Inc... TXINV M PEN PTY PARITY GENERATION LOAD FROM SCDR MSB SHIFT ENABLE T8 TRANSMITTER CONTROL LOGIC SCTE SCTE SCTIE TC TCIE PREAMBLE (ALL ONES) LOOPS SCTIE TC TCIE ENSCI TE Figure 16-4. SCI Transmitter Advance Information 214 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com BREAK (ALL ZEROS) SBK 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description Register Name Read: SCI Control Register 1 (SCC1) Write: Reset: Read: SCI Control Register 2 (SCC2) Write: Reset: Read: SCI Control Register 3 (SCC3) Write: Reset: Read: SCI Status Register 1 (SCS1) Write: Reset: Read: SCI Data Register (SCDR) Write: Reset: Read: SCI Baud Rate Register (SCBR) Write: Reset: Bit 7 LOOPS 0 SCTIE 0 R8 6 ENSCI 0 TCIE 0 T8 U TC 5 TXINV 0 SCRIE 0 R 0 SCRF 4 M 0 ILIE 0 R 0 IDLE 3 WAKE 0 TE 0 ORIE 0 OR 2 ILTY 0 RE 0 NEIE 0 NF 1 PEN 0 RWU 0 FEIE 0 FE Bit 0 PTY 0 SBK 0 PEIE 0 PE Freescale Semiconductor, Inc... U SCTE 1 R7 T7 1 R6 T6 0 R5 T5 0 R4 T4 0 R3 T3 0 R2 T2 0 R1 T1 0 R0 T0 Unaffected by Reset 0 0 SCP1 0 SCP0 0 R 0 SCR2 0 SCR1 0 SCR0 0 0 0 = Unimplemented U = Unaffected R = Reserved Figure 16-5. SCI Transmitter I/O Register Summary Table 16-3. SCI Transmitter I/O Address Summary Register Address SCC1 $0013 SCC2 $0014 SCC3 $0015 SCS1 $0016 SCDR $0018 SCBR $0019 16.5.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 215 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has the following effects on SCI registers: * * * * * * Sets the framing error bit (FE) in SCS1 Sets the SCI receiver full bit (SCRF) in SCS1 Clears the SCI data register (SCDR) Clears the R8 bit in SCC3 Sets the break flag bit (BKF) in SCS2 May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits Freescale Semiconductor, Inc... 16.5.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted. NOTE: When a break sequence is followed immediately by an idle character, this SCI design exhibits a condition in which the break character length is reduced by one half bit time. In this instance, the break sequence will consist of a valid start bit, eight or nine data bits (as defined by the M bit in SCC1) of logic 0 and one half data bit length of logic 0 in the stop bit position followed immediately by the idle character. To ensure a break character of the proper length is transmitted, always queue up a byte of data to be transmitted while the final break sequence is in progress. Advance Information 216 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description NOTE: When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost. A good time to toggle the TE bit for a queued idle character is when the SCTE bit becomes set and just before writing the next byte to the SCDR. 16.5.2.5 Inversion of Transmitted Output The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at logic 1. (See 16.9.1 SCI Control Register 1.) 16.5.2.6 Transmitter Interrupts The following conditions can generate CPU interrupt requests from the SCI transmitter: * SCI transmitter empty (SCTE) -- The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate transmitter CPU interrupt requests. Transmission complete (TC) -- The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. Freescale Semiconductor, Inc... * 16.5.3 Receiver Figure 16-6 shows the structure of the SCI receiver. 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 217 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) INTERNAL BUS SCR1 SCP1 SCP0 SCR2 SCR0 START 0 L RWU PRESCALER BAUD DIVIDER SCI DATA REGISTER STOP /4 CGMXCLK / 16 DATA RECOVERY 11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 RxD H ALL ONES Freescale Semiconductor, Inc... BKF RPF ERROR CPU INTERRUPT REQUEST ALL ZEROS CPU INTERRUPT REQUEST M WAKE ILTY PEN PTY WAKEUP LOGIC PARITY CHECKING IDLE ILIE SCRF SCRIE MSB SCRF IDLE R8 ILIE SCRIE OR ORIE NF NEIE FE FEIE PE PEIE OR ORIE NF NEIE FE FEIE PE PEIE Figure 16-6. SCI Receiver Block Diagram Advance Information 218 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description Register Name SCI Control Register 1 (SCC1) Read: Write: Reset: SCI Control Register 2 (SCC2) Read: Write: Reset: SCI Control Register 3 (SCC3) Read: Write: Reset: SCI Status Register 1 (SCS1) Read: Write: Reset: SCI Status Register 2 (SCS2) Read: Write: Reset: SCI Data Register (SCDR) Read: Write: Reset: SCI Baud Rate Register (SCBR) Read: Write: Reset: Bit 7 LOOPS 0 SCTIE 0 R8 6 ENSCI 0 TCIE 0 T8 U TC 5 TXINV 0 SCRIE 0 R 0 SCRF 4 M 0 ILIE 0 R 0 IDLE 3 WAKE 0 TE 0 ORIE 0 OR 2 ILTY 0 RE 0 NEIE 0 NF 1 PEN 0 RWU 0 FEIE 0 FE Bit 0 PTY 0 SBK 0 PEIE 0 PE Freescale Semiconductor, Inc... U SCTE 1 0 1 0 0 0 0 0 0 0 0 0 0 BKF 0 RPF 0 R7 T7 0 R6 T6 0 R5 T5 0 R4 T4 0 R3 T3 0 R2 T2 0 R1 T1 0 R0 T0 Unaffected by Reset 0 0 SCP1 0 SCP0 0 R 0 SCR2 0 SCR1 0 SCR0 0 0 0 = Unimplemented U = Unaffected R = Reserved Figure 16-7. SCI I/O Receiver Register Summary Table 16-4. SCI Receiver I/O Address Summary Register Address SCC1 $0013 SCC2 $0014 SCC3 $0015 SCS1 $0016 SCS2 $0017 SCDR $0018 SCBR $0019 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 219 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 16.5.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 16.5.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. 16.5.3.3 Data Sampling The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following times (see Figure 16-8): * * After every start bit After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) Freescale Semiconductor, Inc... To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. Advance Information 220 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description RxD START BIT LSB SAMPLES START BIT QUALIFICATION START BIT DATA VERIFICATION SAMPLING RT CLOCK RT CLOCK STATE RT CLOCK RESET RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 Freescale Semiconductor, Inc... Figure 16-8. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 16-5 summarizes the results of the start bit verification samples. Table 16-5. Start Bit Verification RT3, RT5, and RT7 Samples 000 001 010 011 100 101 110 111 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 221 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 16-6 summarizes the results of the data bit samples. Table 16-6. Data Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0 Freescale Semiconductor, Inc... NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 16-7 summarizes the results of the stop bit samples. Table 16-7. Stop Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0 Advance Information 222 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description 16.5.3.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. 16.5.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. Slow Data Tolerance Figure 16-9 shows how much a slow received character can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. Freescale Semiconductor, Inc... MSB STOP RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 DATA SAMPLES Figure 16-9. Slow Data 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 223 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 16-9, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times x 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is 154 - 147 x 100 = 4.54% ------------------------154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 16-9, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 170 - 163 x 100 = 4.12% ------------------------170 Freescale Semiconductor, Inc... Fast Data Tolerance Figure 16-10 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10. STOP IDLE OR NEXT CHARACTER RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 DATA SAMPLES Figure 16-10. Fast Data Advance Information 224 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 16-10, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 154 - 160 x 100 = 3.90%. ------------------------154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 16-10, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 170 - 176 x 100 = 3.53%. ------------------------170 16.5.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: * Address mark -- An address mark is a logic 1 in the most significant bit position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can then compare the character containing the address mark to the user-defined address of the receiver. If they are the same, the receiver remains awake and Advance Information Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 225 Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) processes the characters that follow. If they are not the same, software can set the RWU bit and put the receiver back into the standby state. * Idle input line condition -- When the WAKE bit is clear, an idle character on the RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. Freescale Semiconductor, Inc... NOTE: With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately. 16.5.3.7 Receiver Interrupts The following sources can generate CPU interrupt requests from the SCI receiver: * SCI receiver full (SCRF) -- The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU interrupts. Idle input (IDLE) -- The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in from the RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate CPU interrupt requests. * 16.5.3.8 Error Interrupts The following receiver error flags in SCS1 can generate CPU interrupt requests: * Receiver overrun (OR) -- The OR bit indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR. The previous character Advance Information 226 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Low-Power Modes remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. * Noise flag (NF) -- The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests. Framing error (FE) -- The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests. Parity error (PE) -- The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests. * Freescale Semiconductor, Inc... * 16.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 16.6.1 Wait Mode The SCI module remains active in wait mode. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. 16.6.2 Stop Mode The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. Any enabled CPU interrupt request from the 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 227 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCI module does not bring the MCU out of Stop mode. SCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data. 16.7 SCI During Break Module Interrupts The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See Section 11. Break Module). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. Freescale Semiconductor, Inc... 16.8 I/O Signals Port E shares two of its pins with the SCI module. The two SCI I/O pins are: * * PTE0/SCTxD -- Transmit data PTE1/SCRxD -- Receive data 16.8.1 PTE0/SCTxD (Transmit Data) The PTE0/SCTxD pin is the serial data output from the SCI transmitter. The SCI shares the PTE0/SCTxD pin with port E. When the SCI is Advance Information 228 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers enabled, the PTE0/SCTxD pin is an output regardless of the state of the DDRE2 bit in data direction register E (DDRE). 16.8.2 PTE1/SCRxD (Receive Data) The PTE1/SCRxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/SCRxD pin with port E. When the SCI is enabled, the PTE1/SCRxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE). Freescale Semiconductor, Inc... 16.9 I/O Registers The following I/O registers control and monitor SCI operation: * * * * * * * SCI control register 1 (SCC1) SCI control register 2 (SCC2) SCI control register 3 (SCC3) SCI status register 1 (SCS1) SCI status register 2 (SCS2) SCI data register (SCDR) SCI baud rate register (SCBR) 16.9.1 SCI Control Register 1 SCI control register 1: * * * * * * * * 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Enables loop mode operation Enables the SCI Controls output polarity Controls character length Controls SCI wakeup method Controls idle character detection Enables parity function Controls parity type Advance Information 229 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Address: $0013 Bit 7 6 ENSCI 0 5 TXINV 0 4 M 0 3 WAKE 0 2 ILLTY 0 1 PEN 0 Bit 0 PTY 0 Read: LOOPS Write: Reset: 0 Figure 16-11. SCI Control Register 1 (SCC1) LOOPS -- Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled ENSCI -- Enable SCI Bit This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = SCI enabled 0 = SCI disabled TXINV -- Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted Freescale Semiconductor, Inc... NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits. Advance Information 230 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers M -- Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 16-8).The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters WAKE -- Wakeup Condition Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup ILTY -- Idle Line Type Bit This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit PEN -- Parity Enable Bit This read/write bit enables the SCI parity function. (See Table 16-8). When enabled, the parity function inserts a parity bit in the most significant bit position. (See Table 16-7). Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 231 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) PTY -- Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity. (See Table 16-8). Reset clears the PTY bit. 1 = Odd parity 0 = Even parity NOTE: Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Table 16-8. Character Format Selection Control Bits M 0 1 0 0 1 1 PEN:PTY 0X 0X 10 11 10 11 Start Bits 1 1 1 1 1 1 Data Bits 8 9 7 7 8 8 Character Format Parity None None Even Odd Even Odd Stop Bits 1 1 1 1 1 1 Character Length 10 Bits 11 Bits 10 Bits 10 Bits 11 Bits 11 Bits Freescale Semiconductor, Inc... 16.9.2 SCI Control Register 2 SCI control register 2: * Enables the following CPU interrupt requests: - Enables the SCTE bit to generate transmitter CPU interrupt requests - Enables the TC bit to generate transmitter CPU interrupt requests - Enables the SCRF bit to generate receiver CPU interrupt requests - Enables the IDLE bit to generate receiver CPU interrupt requests Advance Information 232 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers * * * * Address: Enables the transmitter Enables the receiver Enables SCI wakeup Transmits SCI break characters $0014 Bit 7 6 TCIE 0 5 SCRIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0 Freescale Semiconductor, Inc... Read: SCTIE Write: Reset: 0 Figure 16-12. SCI Control Register 2 (SCC2) SCTIE -- SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Setting the SCTIE bit in SCC3 enables the SCTE bit to generate CPU interrupt requests. Reset clears the SCTIE bit. 1 = SCTE enabled to generate CPU interrupt 0 = SCTE not enabled to generate CPU interrupt TCIE -- Transmission Complete Interrupt Enable Bit This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 233 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCRIE -- SCI Receive Interrupt Enable Bit This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Setting the SCRIE bit in SCC3 enables the SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt ILIE -- Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests TE -- Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the TxD returns to the idle condition (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled Freescale Semiconductor, Inc... NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. Advance Information 234 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers RE -- Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RWU -- Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation SBK -- Send Break Bit Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted Freescale Semiconductor, Inc... NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble. 16.9.3 SCI Control Register 3 SCI control register 3: * * Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted. Enables the following interrupts: 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 235 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) - Receiver overrun interrupts - Noise error interrupts - Framing error interrupts - Parity error interrupts Address: $0015 Bit 7 Read: Write: Reset: U U 0 0 R 0 = Reserved 0 0 U = Unaffected 0 R8 T8 R R ORIE NEIE FEIE PEIE 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... = Unimplemented Figure 16-13. SCI Control Register 3 (SCC3) R8 -- Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits. When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 -- Transmitted Bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset has no effect on the T8 bit. Advance Information 236 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers ORIE -- Receiver Overrun Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR. 1 = SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled NEIE -- Receiver Noise Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = SCI error CPU interrupt requests from NE bit enabled 0 = SCI error CPU interrupt requests from NE bit disabled FEIE -- Receiver Framing Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE. 1 = SCI error CPU interrupt requests from FE bit enabled 0 = SCI error CPU interrupt requests from FE bit disabled PEIE -- Receiver Parity Error Interrupt Enable Bit This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE. Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled Freescale Semiconductor, Inc... 16.9.4 SCI Status Register 1 SCI status register 1 contains flags to signal the following conditions: * * * * * * * Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to SCDR complete Receiver input idle Receiver overrun Noisy data Framing error 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 237 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) * Address: Parity error $0016 Bit 7 6 TC 5 SCRF 4 IDLE 3 OR 2 NF 1 FE Bit 0 PE Read: Write: Reset: SCTE 1 1 0 0 0 0 0 0 = Unimplemented Freescale Semiconductor, Inc... Figure 16-14. SCI Status Register 1 (SCS1) SCTE -- SCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register Advance Information 238 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers TC -- Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is cleared automatically when data, preamble, or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress SCRF -- SCI Receiver Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is set the SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF. 1 = Received data available in SCDR 0 = Data not available in SCDR IDLE -- Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an SCI error CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) OR -- Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 239 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing sequence. Figure 16-15 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading the data register. NORMAL FLAG CLEARING SEQUENCE SCRF = 1 SCRF = 0 BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = 1 OR = 1 READ SCDR BYTE 3 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 BYTE 3 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 2 DELAYED FLAG CLEARING SEQUENCE SCRF = 1 OR = 1 SCRF = 0 OR = 1 SCRF = 1 SCRF = 1 OR = 1 SCRF = 0 OR = 0 BYTE 3 Freescale Semiconductor, Inc... BYTE 1 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1 BYTE 2 BYTE 1 BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1 Figure 16-15. Flag Clearing Sequence Advance Information 240 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers NF -- Receiver Noise Flag Bit This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected FE -- Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected PE -- Receiver Parity Error Bit This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 241 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 16.9.5 SCI Status Register 2 SCI status register 2 contains flags to signal the following conditions: * * Address: Break character detected Incoming data $0017 Bit 7 6 0 5 0 4 0 3 0 2 0 1 BKF Bit 0 RPF Freescale Semiconductor, Inc... Read: Write: Reset: 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 16-16. SCI Status Register 2 (SCS2) BKF -- Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading the SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected RPF -- Reception in Progress Flag Bit This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress Advance Information 242 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers 16.9.6 SCI Data Register The SCI data register is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register. Address: $0018 Bit 7 Read: Write: Reset: R7 T7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0 Freescale Semiconductor, Inc... Unaffected by Reset Figure 16-17. SCI Data Register (SCDR) R7/T7:R0/T0 -- Receive/Transmit Data Bits Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018 writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register. NOTE: Do not use read-modify-write instructions on the SCI data register. 16.9.7 SCI Baud Rate Register The baud rate register selects the baud rate for both the receiver and the transmitter. Address: $0019 Bit 7 Read: Write: Reset: 0 0 0 0 R 0 = Reserved 0 0 0 0 6 0 SCP1 SCP0 R SCR2 SCR1 SCR0 5 4 3 2 1 Bit 0 = Unimplemented Figure 16-18. SCI Baud Rate Register (SCBR) 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Advance Information 243 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCP1 and SCP0 -- SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 16-9. Reset clears SCP1 and SCP0. Table 16-9. SCI Baud Rate Prescaling SCP[1:0] 00 01 10 11 Prescaler Divisor (PD) 1 3 4 13 Freescale Semiconductor, Inc... SCR2 - SCR0 -- SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 16-10. Reset clears SCR2-SCR0. Table 16-10. SCI Baud Rate Selection SCR[2:1:0] 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128 Use the following formula to calculate the SCI baud rate: f Crystal Baud rate = ----------------------------------64 x PD x BD where: fCrystal = crystal frequency PD = prescaler divisor BD = baud rate divisor Advance Information 244 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers Table 16-11 shows the SCI baud rates that can be generated with a 4.9152-MHz crystal. Table 16-11. SCI Baud Rate Selection Examples SCP[1:0] 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 Prescaler Divisor (PD) 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 SCR[2:1:0] 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 Baud Rate (fCrystal = 4.9152 MHz) 76,800 38,400 19,200 9600 4800 2400 1200 600 25,600 12,800 6400 3200 1600 800 400 200 19,200 9600 4800 2400 1200 600 300 150 5908 2954 1477 739 369 185 92 46 Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 245 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Freescale Semiconductor, Inc... Advance Information 246 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 17. Serial Peripheral Interface (SPI) 17.1 Contents 17.2 17.3 17.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Pin Name and Register Name Conventions . . . . . . . . . . . . . . 249 Freescale Semiconductor, Inc... 17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 17.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 17.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 17.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 17.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . 254 17.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . 255 17.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . 256 17.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . 257 17.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.7.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 17.8 17.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 264 17.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 17.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 17.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 17.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 17.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .267 17.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 17.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . . 268 17.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . . 269 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 247 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 17.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 17.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 17.13.5 VSS (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 17.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 17.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 17.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . 274 17.14.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Freescale Semiconductor, Inc... 17.2 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 17.3 Features Features of the SPI module include: * * * * * * * Full-Duplex Operation Master and Slave Modes Double-Buffered Operation with Separate Transmit and Receive Registers Four Master Mode Frequencies (Maximum = Bus Frequency / 2) Maximum Slave Mode Frequency = Bus Frequency Serial Clock with Programmable Polarity and Phase Two Separately Enabled Interrupts with CPU Service: - SPRF (SPI Receiver Full) - SPTE (SPI Transmitter Empty) * * * * Advance Information 248 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Mode Fault Error Flag with CPU Interrupt Capability Overflow Error Flag with CPU Interrupt Capability Programmable Wired-OR Mode I2C (Inter-Integrated Circuit) Compatibility 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Pin Name and Register Name Conventions 17.4 Pin Name and Register Name Conventions The generic names of the SPI input/output (I/O) pins are: * * * * SS (slave select) SPSCK (SPI serial clock) MOSI (master out slave in) MISO (master in slave out) Freescale Semiconductor, Inc... The SPI shares four I/O pins with a parallel I/O port. The full name of an SPI pin reflects the name of the shared port pin. Table 17-1 shows the full names of the SPI I/O pins. The generic pin names appear in the text that follows. Table 17-1. Pin Name Conventions SPI Generic Pin Name Full SPI Pin Name MISO PTE5/MISO MOSI PTE6/MOSI SS PTE4/SS SPSCK PTE7/SPSCK The generic names of the SPI I/O registers are: * * * SPI control register (SPCR) SPI status and control register (SPSCR) SPI data register (SPDR) Table 17-2 shows the names and the addresses of the SPI I/O registers. Table 17-2. I/O Register Addresses Register Name SPI Control Register (SPCR) SPI Status and Control Register (SPSCR) SPI Data Register (SPDR) Address $0010 $0011 $0012 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 249 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 17.5 Functional Description Table 17-3 summarizes the SPI I/O registers and Figure 17-1 shows the structure of the SPI module. Table 17-3. SPI I/O Register Summary Addr $0010 Register Name R/W Bit 7 6 R 0 5 SPMSTR 1 4 CPOL 0 3 CPHA 1 2 SPWOM 0 1 SPE 0 Bit 0 SPTIE 0 SPI Control Register Read: SPRIE (SPCR) Write: Reset: 0 Freescale Semiconductor, Inc... $0011 SPI Status and Control Register Read: (SPSCR) Write: Reset: SPRF ERRIE 0 0 OVRF MODF SPTE MODFEN SPR1 0 SPR0 0 0 0 1 0 $0012 SPI Data Register Read: (SPDR) Write: Reset: R7 T7 R6 T6 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 Unaffected by Reset R = Reserved = Unimplemented Advance Information 250 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description INTERNAL BUS TRANSMIT DATA REGISTER BUS CLOCK 7 6 SHIFT REGISTER 5 4 3 2 1 0 MISO /2 CLOCK DIVIDER /8 / 32 / 128 CLOCK SELECT MOSI RECEIVE DATA REGISTER PIN CONTROL LOGIC SPSCK CLOCK LOGIC M S SS Freescale Semiconductor, Inc... SPMSTR SPE SPR1 SPR0 SPMSTR CPHA CPOL TRANSMITTER CPU INTERRUPT REQUEST SPI CONTROL RECEIVER/ERROR CPU INTERRUPT REQUEST MODFEN ERRIE SPTIE SPRIE SPE SPRF SPTE OVRF MODF SPWOM Figure 17-1. SPI Module Block Diagram The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt driven. All SPI interrupts can be serviced by the CPU. The following paragraphs describe the operation of the SPI module. 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 251 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 17.5.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR (SPCR $0010), is set. NOTE: Configure the SPI modules as master and slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. See SPI Control Register on page 271. Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI module by writing to the SPI data register. If the shift register is empty, the byte immediately transfers to the shift register, setting the SPI transmitter empty bit, SPTE (SPSCR $0011). The byte begins shifting out on the MOSI pin under the control of the serial clock. (See Table 17-4). The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See SPI Status and Control Register on page 274). Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. Freescale Semiconductor, Inc... MASTER MCU SLAVE MCU SHIFT REGISTER MISO MISO MOSI MOSI SHIFT REGISTER SPSCK BAUD RATE GENERATOR SPSCK SS VDD SS Figure 17-2. Full-Duplex Master-Slave Connections Advance Information 252 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master's MISO pin. The transmission ends when the receiver full bit, SPRF (SPSCR), becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register and then reading the SPI data register. Writing to the SPI data register clears the SPTIE bit. Freescale Semiconductor, Inc... 17.5.2 Slave Mode The SPI operates in slave mode when the SPMSTR bit (SPCR, $0010) is clear. In slave mode the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave MCU must be at logic 0. SS must remain low until the transmission is complete. (See Mode Fault Error on page 261). In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module. After a byte enters the shift register of a slave SPI, it is transferred to the receive data register, and the SPRF bit (SPSCR) is set. To prevent an overflow condition, slave software then must read the SPI data register before another byte enters the shift register. The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed, which is twice as fast as the fastest master SPSCK clock that can be generated. The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed. When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. Otherwise the byte already in the slave shift register shifts out on the MISO pin. 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 253 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Data written to the slave shift register during a a transmission remains in a buffer until the end of the transmission. When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is clear, the falling edge of SS starts a transmission. (See Transmission Formats on page 254). If the write to the data register is late, the SPI transmits the data already in the shift register from the previous transmission. Freescale Semiconductor, Inc... NOTE: To prevent SPSCK from appearing as a clock edge, SPSCK must be in the proper idle state before the slave is enabled. 17.6 Transmission Formats During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line synchronizes shifting and sampling on the two serial data lines. A slave select line allows individual selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can be used optionally to indicate a multiple-master bus contention. 17.6.1 Clock Phase and Polarity Controls Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. The clock phase (CPHA) control bit (SPCR) selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. NOTE: Before writing to the CPOL bit or the CPHA bit (SPCR), disable the SPI by clearing the SPI enable bit (SPE). 68HC908AZ32A -- Rev 0.0 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com MOTOROLA Advance Information 254 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Transmission Formats 17.6.2 Transmission Format When CPHA = 0 Figure 17-3 shows an SPI transmission in which CPHA (SPCR) is logic 0. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI (see Mode Fault Error on page 261). When CPHA = 0, the first SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low again between each byte transmitted. Freescale Semiconductor, Inc... SCK CYCLE # FOR REFERENCE SCK CPOL = 0 1 2 3 4 5 6 7 8 SCK CPOL = 1 MOSI FROM MASTER MISO FROM SLAVE SS TO SLAVE CAPTURE STROBE MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB Figure 17-3. Transmission Format (CPHA = 0) 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 255 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 17.6.3 Transmission Format When CPHA = 1 Figure 17-4 shows an SPI transmission in which CPHA (SPCR) is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See Mode Fault Error on page 261). When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line. SCK CYCLE # FOR REFERENCE 1 2 3 4 5 6 7 8 Freescale Semiconductor, Inc... SCK CPOL = 0 SCK CPOL =1 MOSI FROM MASTER MISO FROM SLAVE MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB SS TO SLAVE CAPTURE STROBE Figure 17-4. Transmission Format (CPHA = 1) Advance Information 256 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Transmission Formats 17.6.4 Transmission Initiation Latency When the SPI is configured as a master (SPMSTR = 1), transmissions are started by a software write to the SPDR ($0012). CPHA has no effect on the delay to the start of the transmission, but it does affect the initial state of the SCK signal. When CPHA = 0, the SCK signal remains inactive for the first half of the first SCK cycle. When CPHA = 1, the first SCK cycle begins with an edge on the SCK line from its inactive to its active level. The SPI clock rate (selected by SPR1-SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. (See Figure 17-5). The internal SPI clock in the master is a free-running derivative of the internal MCU clock. It is only enabled when both the SPE and SPMSTR bits (SPCR) are set to conserve power. SCK edges occur half way through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR will occur relative to the slower SCK. This uncertainty causes the variation in the initiation delay shown in Figure 17-5. This delay will be no longer than a single SPI bit time. That is, the maximum delay between the write to SPDR and the start of the SPI transmission is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 257 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) WRITE TO SPDR BUS CLOCK MOSI SCK CPHA = 1 SCK CPHA = 0 SCK CYCLE NUMBER INITIATION DELAY MSB BIT 6 BIT 5 Freescale Semiconductor, Inc... 1 2 3 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN WRITE TO SPDR BUS CLOCK EARLIEST LATEST WRITE TO SPDR BUS CLOCK SCK = INTERNAL CLOCK / 8; 8 POSSIBLE START POINTS SCK = INTERNAL CLOCK / 2; 2 POSSIBLE START POINTS WRITE TO SPDR BUS CLOCK WRITE TO SPDR BUS CLOCK Figure 17-5. Transmission Start Delay (Master) EARLIEST EARLIEST EARLIEST LATEST SCK = INTERNAL CLOCK / 32; 32 POSSIBLE START POINTS LATEST SCK = INTERNAL CLOCK / 128; 128 POSSIBLE START POINTS LATEST Advance Information 258 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Error Conditions 17.7 Error Conditions Two flags signal SPI error conditions: 1. Overflow (OVRF in SPSCR) -- Failing to read the SPI data register before the next byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read by accessing the SPI data register. OVRF is in the SPI status and control register. 2. Mode fault error (MODF in SPSCR) -- The MODF bit indicates that the voltage on the slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register. Freescale Semiconductor, Inc... 17.7.1 Overflow Error The overflow flag (OVRF in SPSCR) becomes set if the SPI receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. (See Figure 17-3 and Figure 17-4.) If an overflow occurs, the data being received is not transferred to the receive data register so that the unread data can still be read. Therefore, an overflow error always indicates the loss of data. OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE in SPSCR) is also set. MODF and OVRF can generate a receiver/error CPU interrupt request. (See Figure 17-8). It is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. If an end-of-block transmission interrupt was meant to pull the MCU out of wait, having an overflow condition without overflow interrupts enabled causes the MCU to hang in wait mode. If the OVRF is enabled to generate an interrupt, it can pull the MCU out of wait mode instead. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 17-6 shows how it is possible to miss an overflow. 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 259 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) BYTE 1 1 BYTE 2 4 BYTE 3 6 BYTE 4 8 SPRF OVRF READ SPSCR READ SPDR 1 2 3 4 2 5 3 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. BYTE 2 SETS SPRF BIT. 5 6 7 8 7 CPU READS SPSCRW WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, BUT NOT OVRF BIT. BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS SET. BYTE 4 IS LOST. Freescale Semiconductor, Inc... Figure 17-6. Missed Read of Overflow Condition The first part of Figure 17-6 shows how to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by the second transmission example, the OVRF flag can be set in between the time that SPSCR and SPDR are read. In this case, an overflow can be easily missed. Since no more SPRF interrupts can be generated until this OVRF is serviced, it will not be obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR after the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions will complete with an SPRF interrupt. Figure 17-7 illustrates this process. Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit (SPSCR). Advance Information 260 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Error Conditions BYTE 1 SPI RECEIVE COMPLETE SPRF 1 BYTE 2 5 BYTE 3 7 BYTE 4 11 OVRF 2 4 6 9 8 8 9 12 14 READ SPSCR READ SPDR 1 2 3 4 5 6 7 3 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT. BYTE 2 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. 10 13 Freescale Semiconductor, Inc... CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 12 CPU READS SPSCR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. Figure 17-7. Clearing SPRF When OVRF Interrupt Is Not Enabled 17.7.2 Mode Fault Error For the MODF flag (in SPSCR) to be set, the mode fault error enable bit (MODFEN in SPSCR) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared. MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE in SPSCR) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. MODF and OVRF can generate a receiver/error CPU interrupt request. (See Figure 17-8). It is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 261 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master SPI causes the following events to occur: * * * * * If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request. The SPE bit is cleared. The SPTE bit is set. The SPI state counter is cleared. The data direction register of the shared I/O port regains control of port drivers. Freescale Semiconductor, Inc... NOTE: To prevent bus contention with another master SPI after a mode fault error, clear all data direction register (DDR) bits associated with the SPI shared port pins. Setting the MODF flag (SPSCR) does not clear the SPMSTR bit. Reading SPMSTR when MODF = 1 will indicate a MODE fault error occurred in either master mode or slave mode. When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission. When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK returns to its idle level after the shift of the eighth data bit. When CPHA = 1, the transmission begins when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK returns to its IDLE level after the shift of the last data bit. (See Transmission Formats on page 254). NOTE: NOTE: When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and later deselected (SS is at logic 1) even if no SPSCK is sent to that slave. This happens because SS at logic 0 indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later deselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set. The MODF Advance Information 262 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Interrupts bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by toggling the SPE bit of the slave. NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if a transmission has begun. To clear the MODF flag, read the SPSCR and then write to the SPCR register. This entire clearing procedure must occur with no MODF condition existing or else the flag will not be cleared. Freescale Semiconductor, Inc... 17.8 Interrupts Four SPI status flags can be enabled to generate CPU interrupt requests: Table 17-4. SPI Interrupts Flag SPTE (Transmitter Empty) SPRF (Receiver Full) OVRF (Overflow) MODF (Mode Fault) Request SPI Transmitter CPU Interrupt Request (SPTIE = 1) SPI Receiver CPU Interrupt Request (SPRIE = 1) SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1) SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1, MODFEN = 1) The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests. The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt, provided that the SPI is enabled (SPE = 1). The error interrupt enable bit (ERRIE) enables both the MODF and OVRF flags to generate a receiver/error CPU interrupt request. The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF flag is enabled to generate receiver/error CPU interrupt requests. 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 263 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) SPTE SPTIE SPE SPI TRANSMITTER CPU INTERRUPT REQUEST SPRIE SPRF ERRIE MODF OVRF SPI RECEIVER/ERROR CPU INTERRUPT REQUEST Freescale Semiconductor, Inc... Figure 17-8. SPI Interrupt Request Generation Two sources in the SPI status and control register can generate CPU interrupt requests: 1. SPI receiver full bit (SPRF) -- The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF can generate an SPI receiver/error CPU interrupt request. 2. SPI transmitter empty (SPTE) -- The SPTE bit becomes set every time a byte transfers from the transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE can generate an SPTE CPU interrupt request. 17.9 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates when the transmit data buffer is ready to accept new data. Write to the SPI data register only when the SPTE bit is high. Figure 17-9 shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA:CPOL = 1:0). Advance Information 264 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Resetting the SPI WRITE TO SPDR 1 3 8 SPTE 2 5 10 SPSCK (CPHA:CPOL = 1:0) MOSI MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT 654321 654321 654 BYTE 1 BYTE 2 BYTE 3 4 9 SPRF Freescale Semiconductor, Inc... READ SPSCR 6 11 READ SPDR 1 2 3 4 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT. BYTE 1 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2 AND CLEARING SPTE BIT. FIRST INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. BYTE 2 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. CPU READS SPSCR WITH SPRF BIT SET. 7 8 9 7 CPU READS SPDR, CLEARING SPRF BIT. CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE 3 AND CLEARING SPTE BIT. 12 SECOND INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. 10 BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 11 CPU READS SPSCR WITH SPRF BIT SET. 12 CPU READS SPDR, CLEARING SPRF BIT. 5 6 Figure 17-9. SPRF/SPTE CPU Interrupt Timing For a slave, the transmit data buffer allows back-to-back transmissions to occur without the slave having to time the write of its data between the transmissions. Also, if no new data is written to the data buffer, the last value contained in the shift register will be the next data word transmitted. 17.10 Resetting the SPI Any system reset completely resets the SPI. Partial reset occurs whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the following occurs: 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 265 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) * * * * * The SPTE flag is set. Any transmission currently in progress is aborted. The shift register is cleared. The SPI state counter is cleared, making it ready for a new complete transmission. All the SPI port logic is defaulted back to being general-purpose I/O. Freescale Semiconductor, Inc... The following additional items are reset only by a system reset: * * * All control bits in the SPCR register All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0) The status flags SPRF, OVRF, and MODF By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without having to reset all control bits when SPE is set back to high for the next transmission. By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI also can be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set. 17.11 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 17.11.1 Wait Mode The SPI module remains active after the execution of a WAIT instruction. In wait mode, the SPI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. Advance Information 266 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) SPI During Break Interrupts If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction. To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE). (See Interrupts on page 263). 17.11.2 Stop Mode The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after the MCU exits stop mode. If stop mode is exited by reset, any transfer in progress is aborted and the SPI is reset. Freescale Semiconductor, Inc... 17.12 SPI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR, $FE03) enables software to clear status bits during the break state. (See SIM Break Flag Control Register on page 134). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the data register in break mode will not initiate a transmission nor will this data be transferred into the shift register. 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 267 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect. 17.13 I/O Signals The SPI module has four I/O pins and shares three of them with a parallel I/O port. * * * * * MISO -- Data received MOSI -- Data transmitted SPSCK -- Serial clock SS -- Slave select VSS -- Clock ground Freescale Semiconductor, Inc... The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD. 17.13.1 MISO (Master In/Slave Out) MISO is one of the two SPI module pins that transmit serial data. In full duplex operation, the MISO pin of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin. Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multipleslave system, a logic 1 on the SS pin puts the MISO pin in a highimpedance state. Advance Information 268 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Signals When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction register of the shared I/O port. 17.13.2 MOSI (Master Out/Slave In) MOSI is one of the two SPI module pins that transmit serial data. In full duplex operation, the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin. When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port. Freescale Semiconductor, Inc... 17.13.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port. 17.13.4 SS (Slave Select) The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission. (See 17.6 Transmission Formats.) Since it is used to indicate the start of a transmission, the SS must be toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low throughout the transmission for the CPHA = 1 format. See Figure 17-10. 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 269 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 BYTE 1 BYTE 2 BYTE 3 Figure 17-10. CPHA/SS Timing When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can still prevent the state of the SS from creating a MODF error. (See SPI Status and Control Register on page 274). Freescale Semiconductor, Inc... NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a highimpedance state. The slave SPI ignores all incoming SPSCK clocks, even if a transmission already has begun. When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. (See Mode Fault Error on page 261). For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless of the state of the data direction register of the shared I/O port. The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the data register. (See Table 175). Advance Information 270 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Registers Table 17-5. SPI Configuration SPE SPMSTR MODFEN 0 1 1 1 X 0 1 1 X X 0 1 SPI Configuration Not Enabled Slave Master without MODF Master with MODF State of SS Logic General-Purpose I/O; SS Ignored by SPI Input-Only to SPI General-Purpose I/O; SS Ignored by SPI Input-Only to SPI Freescale Semiconductor, Inc... X = don't care 17.13.5 VSS (Clock Ground) VSS is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. To reduce the ground return path loop and minimize radio frequency (RF) emissions, connect the ground pin of the slave to the VSS pin. 17.14 I/O Registers Three registers control and monitor SPI operation: * * * SPI control register (SPCR $0010) SPI status and control register (SPSCR $0011) SPI data register (SPDR $0012) 17.14.1 SPI Control Register The SPI control register: * * * * Enables SPI module interrupt requests Selects CPU interrupt requests Configures the SPI module as master or slave Selects serial clock polarity and phase 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 271 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) * * Address: Configures the SPSCK, MOSI, and MISO pins as open-drain outputs Enables the SPI module $0010 Bit 7 6 R 0 = Reserved 5 SPMSTR 1 4 CPOL 0 3 CPHA 1 2 SPWOM 0 1 SPE 0 Bit 0 SPTIE 0 Read: SPRIE Write: Reset: 0 R Freescale Semiconductor, Inc... Figure 17-11. SPI Control Register (SPCR) SPRIE -- SPI Receiver Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit. 1 = SPRF CPU interrupt requests enabled 0 = SPRF CPU interrupt requests disabled SPMSTR -- SPI Master Bit This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode CPOL -- Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 17-3 and Figure 17-4.) To transmit data between SPI modules, the SPI modules must have identical CPOL bits. Reset clears the CPOL bit. CPHA -- Clock Phase Bit This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure 17-3 and Figure 17-4.) To transmit data between SPI modules, the SPI modules must have identical Advance Information 272 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Registers CPHA bits. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between bytes. (See Figure 17-10). Reset sets the CPHA bit. When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the data register. Therefore, the slave data register must be loaded with the desired transmit data before the falling edge of SS. Any data written after the falling edge is stored in the data register and transferred to the shift register at the current transmission. When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. The same applies when SS is high for a slave. The MISO pin is held in a high-impedance state, and the incoming SPSCK is ignored. In certain cases, it may also cause the MODF flag to be set. (See Mode Fault Error on page 261). A logic 1 on the SS pin does not in any way affect the state of the SPI state machine. Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 273 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) SPWOM -- SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins SPE -- SPI Enable Bit This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI (see Resetting the SPI on page 265). Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled SPTIE -- SPI Transmit Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit. 1 = SPTE CPU interrupt requests enabled 0 = SPTE CPU interrupt requests disabled Freescale Semiconductor, Inc... 17.14.2 SPI Status and Control Register The SPI status and control register contains flags to signal the following conditions: * * * * Receive data register full Failure to clear SPRF bit before next byte is received (overflow error) Inconsistent logic level on SS pin (mode fault error) Transmit data register empty The SPI status and control register also contains bits that perform these functions: * * * Advance Information 274 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Enable error interrupts Enable mode fault error detection Select master SPI baud rate 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Registers Address: $0011 Bit 7 6 ERRIE 5 OVRF 4 MODF 3 SPTE MODFEN 0 0 1 0 SPR1 0 SPR0 0 2 1 Bit 0 Read: Write: Reset: SPRF 0 R 0 = Reserved = Unimplemented Figure 17-12. SPI Status and Control Register (SPSCR) SPRF -- SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Any read of the SPI data register clears the SPRF bit. Reset clears the SPRF bit. 1 = Receive data register full 0 = Receive data register not full ERRIE -- Error Interrupt Enable Bit This read-only bit enables the MODF and OVRF flags to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests OVRF -- Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next byte enters the shift register. In an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the SPI data register. Reset clears the OVRF flag. 1 = Overflow 0 = No overflow Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 275 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) MODF -- Mode Fault Bit This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission. In a master SPI, the MODF flag is set if the SS pin goes low at any time. Clear the MODF bit by reading the SPI status and control register with MODF set and then writing to the SPI data register. Reset clears the MODF bit. 1 = SS pin at inappropriate logic level 0 = SS pin at appropriate logic level SPTE -- SPI Transmitter Empty Bit This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. SPTE generates an SPTE CPU interrupt request if the SPTIE bit in the SPI control register is set also. Freescale Semiconductor, Inc... NOTE: Do not write to the SPI data register unless the SPTE bit is high. For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE will be set again within two bus cycles since the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. The SPTE indicates when the next write can occur. Reset sets the SPTE bit. 1 = Transmit data register empty 0 = Transmit data register not empty MODFEN -- Mode Fault Enable Bit This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low, then the SS pin is available as a general-purpose I/O. If the MODFEN bit is set, then this pin is not available as a general purpose I/O. When the SPI is enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of MODFEN. (See SS (Slave Select) on page 269). Advance Information 276 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Registers If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. (See Mode Fault Error on page 261). SPR1 and SPR0 -- SPI Baud Rate Select Bits In master mode, these read/write bits select one of four baud rates as shown in Table 17-6. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Table 17-6. SPI Master Baud Rate Selection SPR1:SPR0 00 01 10 11 Baud Rate Divisor (BD) 2 8 32 128 Freescale Semiconductor, Inc... Use this formula to calculate the SPI baud rate: CGMOUT Baud rate = ------------------------2 x BD where: CGMOUT = base clock output of the clock generator module (CGM), see Section 8. Clock Generator Module (CGM). BD = baud rate divisor 17.14.3 SPI Data Register The SPI data register is the read/write buffer for the receive data register and the transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate buffers that can contain different values. See Figure 17-1 68HC908AZ32A -- Rev 0.0 MOTOROLA Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Advance Information 277 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Address: $0012 Bit 7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0 Read: Write: Reset: R7 T7 Indeterminate after Reset Figure 17-13. SPI Data Register (SPDR) R7-R0/T7-T0 -- Receive/Transmit Data Bits Freescale Semiconductor, Inc... NOTE: Do not use read-modify-write instructions on the SPI data register since the buffer read is not the same as the buffer written. Advance Information 278 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 18. Timer Interface Module A (TIMA) 18.1 Contents 18.2 18.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Freescale Semiconductor, Inc... 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.4.1 TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 18.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 285 18.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 286 18.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 287 18.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 288 18.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 289 18.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 18.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 18.7 TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 293 18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 18.8.1 TIMA Clock Pin (PTD6/ATD14/ TACLK) . . . . . . . . . . . . . . 294 18.8.2 TIMA Channel I/O Pins (PTF3/TCH5-PTF0/TCH2 and PTE3/TCH1-PTE2/TCH0) . . . . . . . . . . . . . . . . . . . . . . . . . 294 18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 18.9.1 TIMA Status and Control Register . . . . . . . . . . . . . . . . . . .295 18.9.2 TIMA Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 297 18.9.3 TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 298 18.9.4 TIMA Channel Status and Control Registers . . . . . . . . . . . 299 18.9.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .306 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 279 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) 18.2 Introduction This section describes the timer interface module (TIMA). The TIMA is a 6-channel timer that provides a timing reference with input capture, output compare and pulse-width-modulation functions. Figure 18-1 is a block diagram of the TIMA. 18.3 Features Features of the TIMA include: * Six Input Capture/Output Compare Channels - Rising-Edge, Falling-Edge or Any-Edge Input Capture Trigger - Set, Clear or Toggle Output Compare Action * * Buffered and Unbuffered Pulse Width Modulation (PWM) Signal Generation Programmable TIMA Clock Input - 7 Frequency Internal Bus Clock Prescaler Selection - External TIMA Clock Input (4 MHz Maximum Frequency) * * * Free-Running or Modulo Up-Count Operation Toggle Any Channel Pin on Overflow TIMA Counter Stop and Reset Bits Freescale Semiconductor, Inc... Advance Information 280 68HC908AZ32A -- Rev 0.0 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Features PTD6/ATD14/TCLK INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER TCLK PRESCALER SELECT PRESCALER PS2 PS1 PS0 TOF TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CHANNEL 2 16-BIT COMPARATOR TCH2H:TCH2L 16-BIT LATCH MS2A CHANNEL 3 16-BIT COMPARATOR TCH3H:TCH3L 16-BIT LATCH MS3A CHANNEL 4 16-BIT COMPARATOR TCH4H:TCH4L 16-BIT LATCH MS4A CHANNEL 5 16-BIT COMPARATOR TCH5H:TCH5L 16-BIT LATCH MS5A CH5IE CH5F ELS5B ELS5A MS4B CH4IE TOV5 CH5MAX CH4F ELS4B ELS4A CH3IE TOV4 CH5MAX CH3F ELS3B ELS3A MS2B CH2IE TOV3 CH3MAX CH2F ELS2B ELS2A CH1IE TOV2 CH2MAX CH1F ELS1B ELS1A MS0B CH0IE TOV1 CH1MAX CH0F ELS0B ELS0A TOV0 CH0MAX Freescale Semiconductor, Inc... PTE2 LOGIC INTERRUPT LOGIC PTE2/TCH0 PTE3 LOGIC INTERRUPT LOGIC PTE3/TCH1 PTF0 LOGIC INTERRUPT LOGIC PTF0/TCH2 PTF1 LOGIC INTERRUPT LOGIC PTF1/TCH3 PTF2 LOGIC INTERRUPT LOGIC PTF2/TCH4/TACH4 PTF3 LOGIC INTERRUPT LOGIC PTF3/TCH5/TACH5 Figure 18-1. TIMA Block Diagram 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 281 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Figure 18-2. TIMA I/O Register Summary Addr. $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 Register Name TIMA Status/Control Register (TASC) Reserved TIMA Counter Register High (TACNTH) TIMA Counter Register Low (TACNTL) TIMA Counter Modulo Reg. High (TAMODH) TIMA Counter Modulo Reg. Low (TAMODL) TIMA Ch. 0 Status/Control Register (TASC0) TIMA Ch. 0 Register High (TACH0H) TIMA Ch. 0 Register Low (TACH0L) TIMA Ch. 1 Status/Control Register (TASC1) TIMA Ch. 1 Register High (TACH1H) TIMA Ch. 1 Register Low (TACH1L) TIMA Ch. 2 Status/Control Register (TASC2) TIMA Ch. 2 Register High (TACH2H) TIMA Ch. 2 Register Low (TACH2L) TIMA Ch. 3 Status/Control Register (TASC3) TIMA Ch. 3 Register High (TACH3H) TIMA Ch. 3 Register Low (TACH3L) TIMA Ch. 4 Status/Control Register (TASC4) TIMA Ch. 4 Register High (TACH4H) TIMA Ch. 4 Register Low (TACH4L) TIMA Ch. 5 Status/Control Register (TASC5) TIMA Ch. 5 Register High (TACH5H) TIMA Ch. 5 Register Low (TACH5L) Bit 7 TOF R Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7 CH2F Bit 15 Bit 7 CH3F Bit 15 Bit 7 CH4F Bit 15 Bit 7 CH5F Bit 15 Bit 7 6 TOIE R 14 6 14 6 CH0IE 14 6 CH1IE 14 6 CH2IE 14 6 CH3IE 14 6 CH4IE 14 6 CH5IE 14 6 5 TSTOP R 13 5 13 5 MS0B 13 5 0 13 5 MS2B 13 5 0 13 5 MS4B 13 5 0 13 5 4 TRST R 12 4 12 4 MS0A 12 4 MS1A 12 4 MS2A 12 4 MS3A 12 4 MS4A 12 4 MS5A 12 4 3 0 R 11 3 11 3 ELS0B 11 3 ELS1B 11 3 ELS2B 11 3 ELS3B 11 3 ELS4B 11 3 ELS5B 11 3 2 PS2 R 10 2 10 2 ELS0A 10 2 ELS1A 10 2 ELS2A 10 2 ELS3A 10 2 ELS4A 10 2 ELS5A 10 2 1 PS1 R 9 1 9 1 TOV0 9 1 TOV1 9 1 TOV2 9 1 TOV3 9 1 TOV4 9 1 TOV5 9 1 Bit 0 PS0 R Bit 8 Bit 0 Bit 8 Bit 0 CH0MAX Bit 8 Bit 0 CH1MAX Bit 8 Bit 0 CH2MAX Bit 8 Bit 0 CH3MAX Bit 8 Bit 0 CH4MAX Bit 8 Bit 0 CH5MAX Bit 8 Bit 0 Freescale Semiconductor, Inc... R = Reserved Advance Information 282 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Functional Description 18.4 Functional Description Figure 18-1 shows the TIMA structure. The central component of the TIMA is the 16-bit TIMA counter that can operate as a free-running counter or a modulo up-counter. The TIMA counter provides the timing reference for the input capture and output compare functions. The TIMA counter modulo registers, TAMODH-TAMODL, control the modulo value of the TIMA counter. Software can read the TIMA counter value at any time without affecting the counting sequence. The six TIMA channels are programmable independently as input capture or output compare channels. Freescale Semiconductor, Inc... 18.4.1 TIMA Counter Prescaler The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin, PTD6/ATD14/TCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMA status and control register select the TIMA clock source. 18.4.2 Input Capture An input capture function has three basic parts: edge select logic, an input capture latch and a 16-bit counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The polarity of the active edge is programmable. The level transition which triggers the counter transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TASC0 through TASC5 control registers with x referring to the active channel number). When an active edge occurs on the pin of an input capture channel, the TIMA latches the contents of the TIMA counter into the TIMA channel registers, TACHxH-TACHxL. Input captures can generate TIMA CPU interrupt requests. Software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit. 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 283 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) The result obtained by an input capture will be two more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. The free-running counter contents are transferred to the TIMA channel register (TACHxH-TACHxL see TIMA Channel Registers on page 306) on each proper signal transition regardless of whether the TIMA channel flag (CH0F-CH5F in TASC0-TASC5 registers) is set or clear. When the status flag is set, a CPU interrupt is generated if enabled. The value of the count latched or "captured" is the time of the event. Because this value is stored in the input capture register 2 bus cycles after the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. However, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. By recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. To measure a period, two successive edges of the same polarity are captured. To measure a pulse width, two alternate polarity edges are captured. Software should track the overflows at the 16-bit module counter to extend its range. Another use for the input capture function is to establish a time reference. In this case, an input capture function is used in conjunction with an output compare function. For example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. A number corresponding to the desired delay is added to this captured value and stored to an output compare register (see TIMA Channel Registers on page 306). Because both input captures and output compares are referenced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. Reset does not affect the contents of the TIMA channel register (TACHxH-TACHxL). Freescale Semiconductor, Inc... Advance Information 284 68HC908AZ32A -- Rev 0.0 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Functional Description 18.4.3 Output Compare With the output compare function, the TIMA can generate a periodic pulse with a programmable polarity, duration and frequency. When the counter reaches the value in the registers of an output compare channel, the TIMA can set, clear or toggle the channel pin. Output compares can generate TIMA CPU interrupt requests. 18.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in Output Compare on page 285. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIMA channel registers. An unsynchronized write to the TIMA channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIMA overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIMA may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. When changing to a larger output compare value, enable TIMA overflow interrupts and write the new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. Advance Information Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 285 Freescale Semiconductor, Inc... * 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) 18.4.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTE2/TCH0 pin. The TIMA channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and channel 1. The output compare value in the TIMA channel 0 registers initially controls the output on the PTE2/TCH0 pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (0 or 1) that control the output are the ones written to last. TASC0 controls and monitors the buffered output compare function and TIMA channel 1 status and control register (TASC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O pin. Channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the PTF0/TCH2 pin. The TIMA channel registers of the linked pair alternately control the output. Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel 3. The output compare value in the TIMA channel 2 registers initially controls the output on the PTF0/TCH2 pin. Writing to the TIMA channel 3 registers enables the TIMA channel 3 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (2 or 3) that control the output are the ones written to last. TASC2 controls and monitors the buffered output compare function, and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is set, the channel 3 pin, PTF1/TCH3, is available as a general-purpose I/O pin. Channels 4 and 5 can be linked to form a buffered output compare channel whose output appears on the PTF2/TCH4 pin. The TIMA channel registers of the linked pair alternately control the output. Setting the MS4B bit in TIMA channel 4 status and control register (TASC4) links channel 4 and channel 5. The output compare value in the TIMA channel 4 registers initially controls the output on the PTF2/TCH4 Freescale Semiconductor, Inc... Advance Information 286 68HC908AZ32A -- Rev 0.0 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Functional Description pin. Writing to the TIMA channel 5 registers enables the TIMA channel 5 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (4 or 5) that control the output are the ones written to last. TASC4 controls and monitors the buffered output compare function and TIMA channel 5 status and control register (TASC5) is unused. While the MS4B bit is set, the channel 5 pin, PTF3/TCH5, is available as a general-purpose I/O pin. NOTE: Freescale Semiconductor, Inc... In buffered output compare operation, do not write new output compare values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered output compares. 18.4.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIMA can generate a PWM signal. The value in the TIMA counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIMA counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 18-3 shows, the output compare value in the TIMA channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMA to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMA to set the pin if the state of the PWM pulse is logic 0. 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 287 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) OVERFLOW PERIOD OVERFLOW OVERFLOW PULSE WIDTH PTEx/TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Freescale Semiconductor, Inc... Figure 18-3. PWM Period and Pulse Width The value in the TIMA counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIMA counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000 (see TIMA Status and Control Register on page 295). The value in the TIMA channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMA channel registers produces a duty cycle of 128/256 or 50%. 18.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in Pulse Width Modulation (PWM) on page 287. The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the TIMA channel registers. An unsynchronized write to the TIMA channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIMA overflow interrupt routine to write a new, smaller pulse width value may cause the compare Advance Information 288 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Functional Description to be missed. The TIMA may pass the new value before it is written to the TIMA channel registers. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIMA overflow interrupts and write the new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. Freescale Semiconductor, Inc... * NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 18.4.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTE2/TCH0 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and channel 1. The TIMA channel 0 registers initially control the pulse width on the PTE2/TCH0 pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (0 or 1) that control the pulse width are the ones written to last. TASC0 controls and monitors the buffered PWM function and TIMA channel 1 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 289 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) status and control register (TASC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE3/TCH1, is available as a general-purpose I/O pin. Channels 2 and 3 can be linked to form a buffered PWM channel whose output appears on the PTF0/TCH2 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output. Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel 3. The TIMA channel 2 registers initially control the pulse width on the PTF0/TCH2 pin. Writing to the TIMA channel 3 registers enables the TIMA channel 3 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (2 or 3) that control the pulse width are the ones written to last. TASC2 controls and monitors the buffered PWM function and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is set, the channel 3 pin, PTF1/TCH3, is available as a general-purpose I/O pin. Channels 4 and 5 can be linked to form a buffered PWM channel whose output appears on the PTF2/TCH4 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output. Setting the MS4B bit in TIMA channel 4 status and control register (TASC4) links channel 4 and channel 5. The TIMA channel 4 registers initially control the pulse width on the PTF2/TCH4 pin. Writing to the TIMA channel 5 registers enables the TIMA channel 5 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (4 or 5) that control the pulse width are the ones written to last. TASC4 controls and monitors the buffered PWM function and TIMA channel 5 status and control register (TASC5) is unused. While the MS4B bit is set, the channel 5 pin, PTF3/TCH5, is available as a general-purpose I/O pin. Freescale Semiconductor, Inc... NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered PWM signals. Advance Information 290 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Functional Description 18.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIMA status and control register (TASC): a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP. b. Reset the TIMA counter and prescaler by setting the TIMA reset bit, TRST. 2. In the TIMA counter modulo registers (TAMODH-TAMODL) write the value for the required PWM period. 3. In the TIMA channel x registers (TACHxH-TACHxL) write the value for the required pulse width. 4. In TIMA channel x status and control register (TASCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB-MSxA (see Table 18-2). b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB-ELSxA. The output action on compare must force the output to the complement of the pulse width level (see Table 18-2). Freescale Semiconductor, Inc... NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIMA status control register (TASC) clear the TIMA stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMA channel 0 registers (TACH0H-TACH0L) initially control the buffered PWM output. TIMA status control register 0 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 291 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) (TASC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIMA channel 2 registers (TACH2H-TACH2L) initially control the buffered PWM output. TIMA status control register 2 (TASC2) controls and monitors the PWM signal from the linked channels. MS2B takes priority over MS2A. Setting MS4B links channels 4 and 5 and configures them for buffered PWM operation. The TIMA channel 4 registers (TACH4H-TACH4L) initially control the buffered PWM output. TIMA status control register 4 (TASC4) controls and monitors the PWM signal from the linked channels. MS4B takes priority over MS4A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMA overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output (see TIMA Channel Status and Control Registers on page 299). Freescale Semiconductor, Inc... 18.5 Interrupts The following TIMA sources can generate interrupt requests: * TIMA overflow flag (TOF) -- The TOF bit is set when the TIMA counter reaches the modulo value programmed in the TIMA counter modulo registers. The TIMA overflow interrupt enable bit, TOIE, enables TIMA overflow CPU interrupt requests. TOF and TOIE are in the TIMA status and control register. TIMA channel flags (CH5F-CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIMA CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. * Advance Information 292 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Low-Power Modes 18.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 18.6.1 Wait Mode The TIMA remains active after the execution of a WAIT instruction. In wait mode, the TIMA registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of wait mode. If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA before executing the WAIT instruction. Freescale Semiconductor, Inc... 18.6.2 Stop Mode The TIMA is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIMA counter. TIMA operation resumes when the MCU exits stop mode. 18.7 TIMA During Break Interrupts A break interrupt stops the TIMA counter and inhibits input captures. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state (see SIM Break Flag Control Register on page 134). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 293 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. 18.8 I/O Signals Port D shares one of its pins with the TIMA. Port E shares two of its pins with the TIMA and port F shares four of its pins with the TIMA. PTD6/ATD14/TCLK is an external clock input to the TIMA prescaler. The six TIMA channel I/O pins are PTE2/TCH0, PTE3/TCH1, PTF0/TCH2, PTF1/TCH3, PTF2/TCH4, and PTF3/TCH5. Freescale Semiconductor, Inc... 18.8.1 TIMA Clock Pin (PTD6/ATD14/ TACLK) PTD6/ATD14/TCLK is an external clock input that can be the clock source for the TIMA counter instead of the prescaled internal bus clock. Select the PTD6/ATD14/TCLK input by writing logic 1s to the three prescaler select bits, PS[2:0] (see 18.9.1 TIMA Status and Control Register). The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is: 1 ------------------------------------ + t SU bus frequency The maximum TCLK frequency is the least: 4 MHz or bus frequency / 2. PTD6/ATD14/TCLK is available as a general-purpose I/O pin or ADC channel when not used as the TIMA clock input. When the PTD6/ATD14/TCLK pin is the TIMA clock input, it is an input regardless of the state of the DDRD6 bit in data direction register D. 18.8.2 TIMA Channel I/O Pins (PTF3/TCH5-PTF0/TCH2 and PTE3/TCH1-PTE2/TCH0) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTE2/TCH0, PTF0/TACH2 and Advance Information 294 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) I/O Registers PTF2/TCH4 can be configured as buffered output compare or buffered PWM pins. 18.9 I/O Registers These I/O registers control and monitor TIMA operation: * * * * * TIMA status and control register (TASC) TIMA control registers (TACNTH-TACNTL) TIMA counter modulo registers (TAMODH-TAMODL) TIMA channel status and control registers (TASC0, TASC1, TASC2, TASC3, TASC4 and TASC5) TIMA channel registers (TACH0H-TACH0L, TACH1H-TACH1L, TACH2H-TACH2L, TACH3H-TACH3L, TACH4H-TACH4L and TACH5H-TACH5L) Freescale Semiconductor, Inc... 18.9.1 TIMA Status and Control Register The TIMA status and control register: * * * * * Address: Enables TIMA overflow interrupts Flags TIMA overflows Stops the TIMA counter Resets the TIMA counter Prescales the TIMA counter clock $0020 Bit 7 6 TOIE 5 TSTOP TRST 0 = Reserved 1 0 R 0 0 0 0 4 0 3 0 PS2 PS1 PS0 2 1 Bit 0 Read: Write: Reset: TOF 0 0 R Figure 18-4. TIMA Status and Control Register (TASC) 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 295 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) TOF -- TIMA Overflow Flag Bit This read/write flag is set when the TIMA counter reaches the modulo value programmed in the TIMA counter modulo registers. Clear TOF by reading the TIMA status and control register when TOF is set and then writing a logic 0 to TOF. If another TIMA overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIMA counter has reached modulo value. 0 = TIMA counter has not reached modulo value. TOIE -- TIMA Overflow Interrupt Enable Bit This read/write bit enables TIMA overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIMA overflow interrupts enabled 0 = TIMA overflow interrupts disabled TSTOP -- TIMA Stop Bit This read/write bit stops the TIMA counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMA counter until software clears the TSTOP bit. 1 = TIMA counter stopped 0 = TIMA counter active Freescale Semiconductor, Inc... NOTE: Do not set the TSTOP bit before entering wait mode if the TIMA is required to exit wait mode. Also, when the TSTOP bit is set and input capture mode is enabled, input captures are inhibited until TSTOP is cleared. TRST -- TIMA Reset Bit Setting this write-only bit resets the TIMA counter and the TIMA prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIMA counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIMA counter cleared 0 = No effect Advance Information 296 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) I/O Registers NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMA counter at a value of $0000. PS[2:0] -- Prescaler Select Bits These read/write bits select either the PTD6/ATD14/TCLK pin or one of the seven prescaler outputs as the input to the TIMA counter as Table 18-1 shows. Reset clears the PS[2:0] bits. Table 18-1. Prescaler Selection PS[2:0] 000 001 010 011 100 101 110 111 TIMA Clock Source Internal Bus Clock /1 Internal Bus Clock / 2 Internal Bus Clock / 4 Internal Bus Clock / 8 Internal Bus Clock / 16 Internal Bus Clock / 32 Internal Bus Clock / 64 PTD6/ATD14/TCLK Freescale Semiconductor, Inc... 18.9.2 TIMA Counter Registers The two read-only TIMA counter registers contain the high and low bytes of the value in the TIMA counter. Reading the high byte (TACNTH) latches the contents of the low byte (TACNTL) into a buffer. Subsequent reads of TACNTH do not affect the latched TACNTL value until TACNTL is read. Reset clears the TIMA counter registers. Setting the TIMA reset bit (TRST) also clears the TIMA counter registers. NOTE: If TACNTH is read during a break interrupt, be sure to unlatch TACNTL by reading TACNTL before exiting the break interrupt. Otherwise, TACNTL retains the value latched during the break. 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 297 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Register Name and Address TACNTH -- $0022 Bit 7 Read: Write: Reset: BIT 15 R 0 6 BIT 14 R 0 5 BIT 13 R 0 4 BIT 12 R 0 3 BIT 11 R 0 2 BIT 10 R 0 1 BIT 9 R 0 Bit 0 BIT 8 R 0 Register Name and Address TACNTL -- $0023 Bit 7 Read: Write: Reset: BIT 7 R 0 R 6 BIT 6 R 0 = Reserved 5 BIT 5 R 0 4 BIT 4 R 0 3 BIT 3 R 0 2 BIT 2 R 0 1 BIT 1 R 0 Bit 0 BIT 0 R 0 Freescale Semiconductor, Inc... Figure 18-5. TIMA Counter Registers (TACNTH and TACNTL) 18.9.3 TIMA Counter Modulo Registers The read/write TIMA modulo registers contain the modulo value for the TIMA counter. When the TIMA counter reaches the modulo value, the overflow flag (TOF) becomes set and the TIMA counter resumes counting from $0000 at the next clock. Writing to the high byte (TAMODH) inhibits the TOF bit and overflow interrupts until the low byte (TAMODL) is written. Reset sets the TIMA counter modulo registers. Advance Information 298 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) I/O Registers Register Name and Address TAMODH -- $0024 Bit 7 Read: BIT 15 Write: Reset: 1 1 1 1 1 1 1 1 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 6 5 4 3 2 1 Bit 0 Register Name and Address TAMODL -- $0025 Bit 7 Read: BIT 7 Write: Reset: 1 1 1 1 1 1 1 1 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 18-6. TIMA Counter Modulo Registers (TAMODH and TAMODL) NOTE: Reset the TIMA counter before writing to the TIMA counter modulo registers. 18.9.4 TIMA Channel Status and Control Registers Each of the TIMA channel status and control registers: * * * * * * * * Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare or PWM operation Selects high, low or toggling output on output compare Selects rising edge, falling edge or any edge as the active input capture trigger Selects output toggling on TIMA overflow Selects 0% and 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 299 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Register Name and Address TASC0 -- $0026 Bit 7 Read: Write: Reset: CH0F CH0IE 0 0 0 0 0 0 0 0 0 MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 6 5 4 3 2 1 Bit 0 Register Name and Address TASC1 -- $0029 Bit 7 Read: Write: Reset: CH1F CH1IE 0 0 R 0 = Reserved R 0 0 0 0 0 0 6 5 0 MS1A ELS1B ELS1A TOV1 CH1MAX 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 18-7. TIMA Channel Status and Control Registers (TASC0-TASC5) Advance Information 300 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) I/O Registers Register Name and Address TASC0 -- $0026 Bit 7 Read: Write: Reset: CH0F CH0IE 0 0 0 0 0 0 0 0 0 MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 6 5 4 3 2 1 Bit 0 Register Name and Address TASC1 -- $0029 Bit 7 Read: Write: Reset: CH1F CH1IE 0 0 R 0 = Reserved R 0 0 0 0 0 0 6 5 0 MS1A ELS1B ELS1A TOV1 CH1MAX 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 18-7. TIMA Channel Status and Control Registers (TASC0-TASC5) 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 301 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Register Name and Address TASC2 -- $002C Bit 7 Read: Write: Reset: CH2F CH2IE 0 0 0 0 0 0 0 0 0 MS2B MS2A ELS2B ELS2A TOV2 CH2MAX 6 5 4 3 2 1 Bit 0 Register Name and Address TASC3 -- $002F Bit 7 Read: Write: Reset: CH3F CH3IE 0 0 0 R 0 0 0 0 0 0 6 5 0 MS3A ELS3B ELS3A TOV3 CH3MAX 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Register Name and Address TASC4 -- $0032 Bit 7 Read: Write: Reset: CH4F CH4IE 0 0 0 0 0 0 0 0 0 MS4B MS4A ELS4B ELS4A TOV4 CH4MAX 6 5 4 3 2 1 Bit 0 Register Name and Address TASC5 -- $0035 Bit 7 Read: Write: Reset: CH5F CH5IE 0 0 R 0 = Reserved R 0 0 0 0 0 0 6 5 0 MS5A ELS5B ELS5A TOV5 CH5MAX 4 3 2 1 Bit 0 Figure 18-7. TIMA Channel Status and Control Registers (TASC0-TASC5) (Continued) Advance Information 302 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) I/O Registers CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIMA counter registers matches the value in the TIMA channel x registers. When CHxIE = 1, clear CHxF by reading TIMA channel x status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIMA CPU interrupts on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMA channel 0, TIMA channel 2 and TIMA channel 4 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TACH1 pin to general-purpose I/O. Setting MS2B disables the channel 3 status and control register and reverts TACH3 pin to general-purpose I/O. Setting MS4B disables the channel 5 status and control register and reverts TACH5 pin to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 303 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) MSxA -- Mode Select Bit A When ELSxB:A 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 18-2. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TACHx pin once PWM, output compare mode or input capture mode is enabled. See Table 18-2. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high Freescale Semiconductor, Inc... NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIMA status and control register (TASC). ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port E or port F and pin PTEx/TACHx or pin PTFx/TACHx is available as a general-purpose I/O pin. However, channel x is at a state determined by these bits and becomes transparent to the respective pin when PWM, input capture mode or output compare operation mode is enabled. Table 18-2 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Advance Information 304 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) I/O Registers Table 18-2. Mode, Edge, and Level Selection MSxB:MSxA X0 ELSxB:ELSxA 00 Output Preset X1 00 00 00 01 01 01 1X 1X 1X 00 01 10 11 01 10 11 01 10 11 Output Compare or PWM Buffered Output Compare or Buffered PWM Input Capture Mode Configuration Pin under Port Control; Initialize Timer Output Level High Pin under Port Control; Initialize Timer Output Level Low Capture on Rising Edge Only Capture on Falling Edge Only Capture on Rising or Falling Edge Toggle Output on Compare Clear Output on Compare Set Output on Compare Toggle Output on Compare Clear Output on Compare Set Output on Compare Freescale Semiconductor, Inc... NOTE: Before enabling a TIMA channel register for input capture operation, make sure that the PTEx/TACHx pin or PTFx/TACHx pin is stable for at least two bus clocks. TOVx -- Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIMA counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIMA counter overflow. 0 = Channel x pin does not toggle on TIMA counter overflow. NOTE: When TOVx is set, a TIMA counter overflow takes precedence over a channel x output compare if both occur at the same time. 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 305 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 18-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW Freescale Semiconductor, Inc... PERIOD PTEx/TCHx OUTPUT COMPARE CHxMAX OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 18-8. CHxMAX Latency 18.9.5 TIMA Channel Registers These read/write registers contain the captured TIMA counter value of the input capture function or the output compare value of the output compare function. The state of the TIMA channel registers after reset is unknown. In input capture mode (MSxB-MSxA = 0:0) reading the high byte of the TIMA channel x registers (TACHxH) inhibits input captures until the low byte (TACHxL) is read. In output compare mode (MSxB-MSxA 0:0) writing to the high byte of the TIMA channel x registers (TACHxH) inhibits output compares and the CHxF bit until the low byte (TACHxL) is written. Advance Information 306 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) I/O Registers Register Name and Address TACH0H -- $0027 Bit 7 Read: Bit 15 Write: Reset: Indeterminate after Reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 6 5 4 3 2 1 Bit 0 Register Name and Address TACH0L -- $0028 Bit 7 Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Register Name and Address TACH1H -- $002A Bit 7 Read: Bit 15 Write: Reset: Indeterminate after Reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 6 5 4 3 2 1 Bit 0 Register Name and Address TACH1L -- $002B Bit 7 Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 Register Name and Address TACH2H -- $002D Bit 7 Read: Bit 15 Write: Reset: Indeterminate after Reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 6 5 4 3 2 1 Bit 0 Figure 18-9. TIMA Channel Registers (TACH0H/L-TACH5H/L) (Sheet 1 of 3) 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 307 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Register Name and Address TACH2L -- $002E Bit 7 Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 Register Name and Address TACH3H -- $0030 Bit 7 Read: Bit 15 Write: Reset: Indeterminate after Reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Register Name and Address TACH3L -- $0031 Bit 7 Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 Register Name and Address TACH4H -- $0033 Bit 7 Read: Bit 15 Write: Reset: Indeterminate after Reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 6 5 4 3 2 1 Bit 0 Register Name and Address TACH4L -- $0034 Bit 7 Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 Figure 18-9. TIMA Channel Registers (TACH0H/L-TACH5H/L) (Sheet 2 of 3) Advance Information 308 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) I/O Registers Register Name and Address TACH5H -- $0036 Bit 7 Read: Bit 15 Write: Reset: Indeterminate after Reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 6 5 4 3 2 1 Bit 0 Register Name and Address TACH5L -- $0037 Bit 7 Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 18-9. TIMA Channel Registers (TACH0H/L-TACH5H/L) (Sheet 3 of 3) 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com Advance Information 309 Freescale Semiconductor, Inc. Timer Interface Module A (TIMA) Freescale Semiconductor, Inc... Advance Information 310 Timer Interface Module A (TIMA) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 19. Timer Interface Module B (TIMB) 19.1 Contents 19.2 19.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Freescale Semiconductor, Inc... 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 19.4.1 TIMB Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . 314 19.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 19.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 19.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 316 19.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 317 19.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 318 19.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 319 19.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 320 19.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 19.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 19.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 19.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 19.7 TIMB During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 323 19.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 19.8.1 TIMB Clock Pin (PTD4/ATD12) . . . . . . . . . . . . . . . . . . . . . 323 19.8.2 TIMB Channel I/O Pins (PTF5/TBCH1-PTF4). . . . . . . . . . 324 19.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 19.9.1 TIMB Status and Control Register . . . . . . . . . . . . . . . . . . .324 19.9.2 TIMB Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 327 19.9.3 TIMB Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 328 19.9.4 TIMB Channel Status and Control Registers . . . . . . . . . . . 328 19.9.5 TIMB Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .333 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Advance Information 311 Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) 19.2 Introduction This section describes the timer interface module (TIMB). The TIMB is a 2-channel timer that provides a timing reference with input capture, output compare and pulse width modulation functions. Figure 19-1 is a block diagram of the TIMB. Freescale Semiconductor, Inc... 19.3 Features Features of the TIMB include: * Two Input Capture/Output Compare Channels - Rising-Edge, Falling-Edge or Any-Edge Input Capture Trigger - Set, Clear or Toggle Output Compare Action * * Buffered and Unbuffered Pulse Width Modulation (PWM) Signal Generation Programmable TIMB Clock Input - 7 Frequency Internal Bus Clock Prescaler Selection - External TIMB Clock Input (4 MHz Maximum Frequency) * * * Free-Running or Modulo Up-Count Operation Toggle Any Channel Pin on Overflow TIMB Counter Stop and Reset Bits Advance Information 312 Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) Features PTD4/ATD12 INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER TCLK PRESCALER SELECT PRESCALER PS2 PS1 PS0 TOF TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CH1IE CH1F ELS1B ELS1A MS0B CH0IE TOV1 CH1MAX CH0F ELS0B ELS0A TOV0 CH0MAX Freescale Semiconductor, Inc... PTF4 LOGIC INTERRUPT LOGIC PTF4 PTF5 LOGIC INTERRUPT LOGIC PTF5/TBCH1 Figure 19-1. TIMB Block Diagram Figure 19-2. TIMB I/O Register Summary Addr. $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 Register Name TIMB Status/Control Register (TBSC) TIMB Counter Register High (TBCNTH) TIMB Counter Register Low (TBCNTL) TIMB Counter Modulo Reg. High (TBMODH) TIMB Counter Modulo Reg. Low (TBMODL) TIMB Ch. 0 Status/Control Register (TBSC0) TIMB Ch. 0 Register High (TBCH0H) TIMB Ch. 0 Register Low (TBCH0L) Bit 7 TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 6 TOIE 14 6 14 6 CH0IE 14 6 5 TSTOP 13 5 13 5 MS0B 13 5 4 TRST 12 4 12 4 MS0A 12 4 3 0 11 3 11 3 ELS0B 11 3 2 PS2 10 2 10 2 ELS0A 10 2 1 PS1 9 1 9 1 TOV0 9 1 Bit 0 PS0 Bit 8 Bit 0 Bit 8 Bit 0 CH0MAX Bit 8 Bit 0 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Advance Information 313 Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) Figure 19-2. TIMB I/O Register Summary Addr. $0048 $0049 $004A Register Name TIMB Ch. 1 Status/Control Register (TBSC1) TIMB Ch. 1 Register High (TBCH1H) TIMB Ch. 1 Register Low (TBCH1L) Bit 7 CH1F Bit 15 Bit 7 6 CH1IE 14 6 5 0 13 5 4 MS1A 12 4 3 ELS1B 11 3 2 ELS1A 10 2 1 TOV1 9 1 Bit 0 CH1MAX Bit 8 Bit 0 R = Reserved Freescale Semiconductor, Inc... 19.4 Functional Description Figure 19-1 shows the TIMB structure. The central component of the TIMB is the 16-bit TIMB counter that can operate as a free-running counter or a modulo up-counter. The TIMB counter provides the timing reference for the input capture and output compare functions. The TIMB counter modulo registers, TBMODH-TBMODL, control the modulo value of the TIMB counter. Software can read the TIMB counter value at any time without affecting the counting sequence. The two TIMB channels are programmable independently as input capture or output compare channels. 19.4.1 TIMB Counter Prescaler The TIMB clock source can be one of the seven prescaler outputs or the TIMB clock pin, PTD4/ATD12. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMB status and control register select the TIMB clock source. 19.4.2 Input Capture An input capture function has three basic parts: edge select logic, an input capture latch and a 16-bit counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The polarity of the active edge is Advance Information 314 Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) Functional Description programmable. The level transition which triggers the counter transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TBSC0 through TBSC1 control registers with x referring to the active channel number). When an active edge occurs on the pin of an input capture channel, the TIMB latches the contents of the TIMB counter into the TIMB channel registers, TBCHxH-TBCHxL. Input captures can generate TIMB CPU interrupt requests. Software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit. The result obtained by an input capture will be two more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. The free-running counter contents are transferred to the TIMB channel register (TBCHxH-TBCHxL, see TIMB Channel Registers on page 333) on each proper signal transition regardless of whether the TIMB channel flag (CH0F-CH1F in TBSC0-TBSC1 registers) is set or clear. When the status flag is set, a CPU interrupt is generated if enabled. The value of the count latched or "captured" is the time of the event. Because this value is stored in the input capture register 2 bus cycles after the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. However, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. By recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. To measure a period, two successive edges of the same polarity are captured. To measure a pulse width, two alternate polarity edges are captured. Software should track the overflows at the 16-bit module counter to extend its range. Another use for the input capture function is to establish a time reference. In this case, an input capture function is used in conjunction with an output compare function. For example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. A number corresponding to the desired delay is added to 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Advance Information 315 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) this captured value and stored to an output compare register (see TIMB Channel Registers on page 333). Because both input captures and output compares are referenced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. Reset does not affect the contents of the input capture channel register (TBCHxH-TBCHxL). Freescale Semiconductor, Inc... 19.4.3 Output Compare With the output compare function, the TIMB can generate a periodic pulse with a programmable polarity, duration and frequency. When the counter reaches the value in the registers of an output compare channel, the TIMB can set, clear or toggle the channel pin. Output compares can generate TIMB CPU interrupt requests. 19.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in Output Compare on page 316. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIMB channel registers. An unsynchronized write to the TIMB channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIMB overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIMB may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: Advance Information 316 Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) Functional Description * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. When changing to a larger output compare value, enable TIMB overflow interrupts and write the new value in the TIMB overflow interrupt routine. The TIMB overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. * Freescale Semiconductor, Inc... 19.4.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTF4 pin. The TIMB channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and channel 1. The output compare value in the TIMB channel 0 registers initially controls the output on the PTF4 pin. Writing to the TIMB channel 1 registers enables the TIMB channel 1 registers to synchronously control the output after the TIMB overflows. At each subsequent overflow, the TIMB channel registers (0 or 1) that control the output are the ones written to last. TBSC0 controls and monitors the buffered output compare function and TIMB channel 1 status and control register (TBSC1) is unused. While the MS0B bit is set, the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O pin. NOTE: In buffered output compare operation, do not write new output compare values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered output compares. 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Advance Information 317 Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) 19.4.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIMB can generate a PWM signal. The value in the TIMB counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIMB counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 19-3 shows, the output compare value in the TIMB channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMB to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMB to set the pin if the state of the PWM pulse is logic 0. OVERFLOW PERIOD OVERFLOW OVERFLOW Freescale Semiconductor, Inc... PULSE WIDTH PTEx/TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 19-3. PWM Period and Pulse Width The value in the TIMB counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIMB counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000 (see 19.9.1 TIMB Status and Control Register). The value in the TIMB channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMB channel registers produces a duty cycle of 128/256 or 50%. Advance Information 318 Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) Functional Description 19.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in Pulse Width Modulation (PWM) on page 318. The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the TIMB channel registers. An unsynchronized write to the TIMB channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIMB overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIMB may pass the new value before it is written to the TIMB channel registers. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIMB overflow interrupts and write the new value in the TIMB overflow interrupt routine. The TIMB overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. Freescale Semiconductor, Inc... * NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Advance Information 319 Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) 19.4.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTF4 pin. The TIMB channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and channel 1. The TIMB channel 0 registers initially control the pulse width on the PTF4 pin. Writing to the TIMB channel 1 registers enables the TIMB channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMB channel registers (0 or 1) that control the pulse width are the ones written to last. TBSC0 controls and monitors the buffered PWM function, and TIMB channel 1 status and control register (TBSC1) is unused. While the MS0B bit is set, the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O pin. Freescale Semiconductor, Inc... NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered PWM signals. 19.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIMB status and control register (TBSC): a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP. b. Reset the TIMB counter and prescaler by setting the TIMB reset bit, TRST. 2. In the TIMB counter modulo registers (TBMODH-TBMODL) write the value for the required PWM period. 3. In the TIMB channel x registers (TBCHxH-TBCHxL) write the value for the required pulse width. 4. In TIMB channel x status and control register (TBSCx): Advance Information 320 Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) Functional Description a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB-MSxA (see Table 19-2). b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB-ELSxA. The output action on compare must force the output to the complement of the pulse width level (see Table 19-2). Freescale Semiconductor, Inc... NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIMB status control register (TBSC) clear the TIMB stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMB channel 0 registers (TBCH0H-TBCH0L) initially control the buffered PWM output. TIMB status control register 0 (TBSC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMB overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output (see TIMB Channel Status and Control Registers on page 328). 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Advance Information 321 Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) 19.5 Interrupts The following TIMB sources can generate interrupt requests: * TIMB overflow flag (TOF) -- The TOF bit is set when the TIMB counter value rolls over to $0000 after matching the value in the TIMB counter modulo registers. The TIMB overflow interrupt enable bit, TOIE, enables TIMB overflow CPU interrupt requests. TOF and TOIE are in the TIMB status and control register. TIMB channel flags (CH1F-CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIMB CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. * Freescale Semiconductor, Inc... 19.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 19.6.1 Wait Mode The TIMB remains active after the execution of a WAIT instruction. In wait mode, the TIMB registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIMB can bring the MCU out of wait mode. If TIMB functions are not required during wait mode, reduce power consumption by stopping the TIMB before executing the WAIT instruction. 19.6.2 Stop Mode The TIMB is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIMB counter. TIMB operation resumes when the MCU exits stop mode. Advance Information 322 Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) TIMB During Break Interrupts 19.7 TIMB During Break Interrupts A break interrupt stops the TIMB counter and inhibits input captures. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state (see SIM Break Flag Control Register on page 134). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. Freescale Semiconductor, Inc... 19.8 I/O Signals Port D shares one of its pins with the TIMB. Port F shares two of its pins with the TIMB. PTD4/ATD12 is an external clock input to the TIMB prescaler. The two TIMB channel I/O pins are PTF4 and PTF5/TBCH1. 19.8.1 TIMB Clock Pin (PTD4/ATD12) PTD4/ATD12 is an external clock input that can be the clock source for the TIMB counter instead of the prescaled internal bus clock. Select the PTD4/ATD12 input by writing logic 1s to the three prescaler select bits, PS[2:0] (see 19.9.1 TIMB Status and Control Register). The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is: 1 ------------------------------------ + t SU bus frequency 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Advance Information 323 Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) The maximum TCLK frequency is the least: 4 MHz or bus frequency / 2. PTD4/ATD12 is available as a general-purpose I/O pin or ADC channel when not used as the TIMB clock input. When the PTD4/ATD12 pin is the TIMB clock input, it is an input regardless of the state of the DDRD4 bit in data direction register D. 19.8.2 TIMB Channel I/O Pins (PTF5/TBCH1-PTF4) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTF4 and PTF5/TBCH1 can be configured as buffered output compare or buffered PWM pins. Freescale Semiconductor, Inc... 19.9 I/O Registers These I/O registers control and monitor TIMB operation: * * * * * TIMB status and control register (TBSC) TIMB control registers (TBCNTH-TBCNTL) TIMB counter modulo registers (TBMODH-TBMODL) TIMB channel status and control registers (TBSC0 and TBSC1) TIMB channel registers (TBCH0H-TBCH0L, TBCH1H-TBCH1L) 19.9.1 TIMB Status and Control Register The TIMB status and control register: * * * * * Enables TIMB overflow interrupts Flags TIMB overflows Stops the TIMB counter Resets the TIMB counter Prescales the TIMB counter clock Advance Information 324 Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) I/O Registers Address: $0040 Bit 7 6 TOIE 5 TSTOP TRST 0 = Reserved 1 0 R 0 0 0 0 4 0 3 0 PS2 PS1 PS0 2 1 Bit 0 Read: Write: Reset: TOF 0 0 R Freescale Semiconductor, Inc... Figure 19-4. TIMB Status and Control Register (TBSC) TOF -- TIMB Overflow Flag Bit This read/write flag is set when the TIMB counter resets to $0000 after reaching the modulo value programmed in the TIMB counter modulo registers. Clear TOF by reading the TIMB status and control register when TOF is set and then writing a logic 0 to TOF. If another TIMB overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIMB counter has reached modulo value 0 = TIMB counter has not reached modulo value TOIE -- TIMB Overflow Interrupt Enable Bit This read/write bit enables TIMB overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIMB overflow interrupts enabled 0 = TIMB overflow interrupts disabled TSTOP -- TIMB Stop Bit This read/write bit stops the TIMB counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMB counter until software clears the TSTOP bit. 1 = TIMB counter stopped 0 = TIMB counter active 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Advance Information 325 Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) NOTE: Do not set the TSTOP bit before entering wait mode if the TIMB is required to exit wait mode. Also, when the TSTOP bit is set and the timer is configured for input capture operation, input captures are inhibited until TSTOP is cleared. TRST -- TIMB Reset Bit Setting this write-only bit resets the TIMB counter and the TIMB prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIMB counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIMB counter cleared 0 = No effect Freescale Semiconductor, Inc... NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMB counter at a value of $0000. PS[2:0] -- Prescaler Select Bits These read/write bits select either the PTD4/ATD12 pin or one of the seven prescaler outputs as the input to the TIMB counter as Table 191 shows. Reset clears the PS[2:0] bits. Table 19-1. Prescaler Selection PS[2:0] 000 001 010 011 100 101 110 111 TIMB Clock Source Internal Bus Clock /1 Internal Bus Clock / 2 Internal Bus Clock / 4 Internal Bus Clock / 8 Internal Bus Clock / 16 Internal Bus Clock / 32 Internal Bus Clock / 64 PTD4/ATD12 Advance Information 326 Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) I/O Registers 19.9.2 TIMB Counter Registers The two read-only TIMB counter registers contain the high and low bytes of the value in the TIMB counter. Reading the high byte (TBCNTH) latches the contents of the low byte (TBCNTL) into a buffer. Subsequent reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL is read. Reset clears the TIMB counter registers. Setting the TIMB reset bit (TRST) also clears the TIMB counter registers. NOTE: Freescale Semiconductor, Inc... If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL by reading TBCNTL before exiting the break interrupt. Otherwise, TBCNTL retains the value latched during the break. Register Name and Address TBCNTH -- $0041 Bit 7 Read: Write: Reset: BIT 15 R 0 6 BIT 14 R 0 5 BIT 13 R 0 4 BIT 12 R 0 3 BIT 11 R 0 2 BIT 10 R 0 1 BIT 9 R 0 Bit 0 BIT 8 R 0 Register Name and Address TBCNTL -- $0042 Bit 7 Read: Write: Reset: BIT 7 R 0 R 6 BIT 6 R 0 R = Reserved 5 BIT 5 R 0 4 BIT 4 R 0 3 BIT 3 R 0 2 BIT 2 R 0 1 BIT 1 R 0 Bit 0 BIT 0 R 0 Figure 19-5. TIMB Counter Registers (TBCNTH and TBCNTL) 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Advance Information 327 Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) 19.9.3 TIMB Counter Modulo Registers The read/write TIMB modulo registers contain the modulo value for the TIMB counter. When the TIMB counter reaches the modulo value, the overflow flag (TOF) becomes set and the TIMB counter resumes counting from $0000 at the next clock. Writing to the high byte (TBMODH) inhibits the TOF bit and overflow interrupts until the low byte (TBMODL) is written. Reset sets the TIMB counter modulo registers. Register Name and Address TBMODH -- $0043 Bit 7 Read: BIT 15 Write: Reset: 1 1 1 1 1 1 1 1 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Register Name and Address TBMODL -- $0044 Bit 7 Read: BIT 7 Write: Reset: 1 1 1 1 1 1 1 1 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 6 5 4 3 2 1 Bit 0 Figure 19-6. TIMB Counter Modulo Registers (TBMODH and TBMODL) NOTE: Reset the TIMB counter before writing to the TIMB counter modulo registers. 19.9.4 TIMB Channel Status and Control Registers Each of the TIMB channel status and control registers: * * * * Advance Information 328 Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare or PWM operation Selects high, low or toggling output on output compare 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) I/O Registers * * * * Selects rising edge, falling edge or any edge as the active input capture trigger Selects output toggling on TIMB overflow Selects 0% and 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation Register Name and Address TBSC0 -- $0045 Bit 7 Read: Write: Reset: CH0F CH0IE 0 0 0 0 0 0 0 0 0 MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Register Name and Address TBSC1 -- $0048 Bit 7 Read: Write: Reset: CH1F CH1IE 0 0 R 0 R = Reserved R 0 0 0 0 0 0 6 5 0 MS1A ELS1B ELS1A TOV1 CH1MAX 4 3 2 1 Bit 0 Figure 19-7. TIMB Channel Status and Control Registers (TBSC0-TBSC1) 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Advance Information 329 Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIMB counter registers matches the value in the TIMB channel x registers. When CHxIE = 1, clear CHxF by reading TIMB channel x status and control register with CHxF set, and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIMB CPU interrupts on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMB channel 0. Setting MS0B disables the channel 1 status and control register and reverts TBCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled Freescale Semiconductor, Inc... Advance Information 330 68HC908AZ32A -- Rev 0.0 Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) I/O Registers MSxA -- Mode Select Bit A When ELSxB:A 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation (see Table 19-2). 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TBCHx pin once PWM, input capture or output compare operation is enabled (see Table 19-2). Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high Freescale Semiconductor, Inc... NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIMB status and control register (TBSC). ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port F and pin PTFx/TBCHx is available as a general-purpose I/O pin. However, channel x is at a state determined by these bits and becomes transparent to the respective pin when PWM, input capture, or output compare mode is enabled. Table 19-2 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Advance Information 331 Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) Table 19-2. Mode, Edge, and Level Selection MSxB:MSxA X0 ELSxB:ELSxA 00 Output Preset X1 00 00 00 01 01 01 1X 1X 1X 00 01 10 11 01 10 11 01 10 11 Output Compare or PWM Buffered Output Compare or Buffered PWM Input Capture Mode Configuration Pin under Port Control; Initialize Timer Output Level High Pin under Port Control; Initialize Timer Output Level Low Capture on Rising Edge Only Capture on Falling Edge Only Capture on Rising or Falling Edge Toggle Output on Compare Clear Output on Compare Set Output on Compare Toggle Output on Compare Clear Output on Compare Set Output on Compare Freescale Semiconductor, Inc... NOTE: Before enabling a TIMB channel register for input capture operation, make sure that the PTFx/TBCHx pin is stable for at least two bus clocks. TOVx -- Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIMB counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIMB counter overflow. 0 = Channel x pin does not toggle on TIMB counter overflow. NOTE: When TOVx is set, a TIMB counter overflow takes precedence over a channel x output compare if both occur at the same time. Advance Information 332 Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) I/O Registers CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 19-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW Freescale Semiconductor, Inc... PERIOD PTEx/TCHx OUTPUT COMPARE CHxMAX OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 19-8. CHxMAX Latency 19.9.5 TIMB Channel Registers These read/write registers contain the captured TIMB counter value of the input capture function or the output compare value of the output compare function. The state of the TIMB channel registers after reset is unknown. In input capture mode (MSxB-MSxA = 0:0) reading the high byte of the TIMB channel x registers (TBCHxH) inhibits input captures until the low byte (TBCHxL) is read. In output compare mode (MSxB-MSxA 0:0) writing to the high byte of the TIMB channel x registers (TBCHxH) inhibits output compares and the CHxF bit until the low byte (TBCHxL) is written. 68HC908AZ32A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com Advance Information 333 Freescale Semiconductor, Inc. Timer Interface Module B (TIMB) Register Name and Address TBCH0H -- $0046 Bit 7 Read: Bit 15 Write: Reset: Indeterminate after Reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 6 5 4 3 2 1 Bit 0 Register Name and Address TBCH0L -- $0047 Bit 7 Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Register Name and Address TBCH1H -- $0049 Bit 7 Read: Bit 15 Write: Reset: Indeterminate after Reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 6 5 4 3 2 1 Bit 0 Register Name and Address TBCH1L -- $004A Bit 7 Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 Figure 19-9. TIMB Channel Registers (TBCH0H/L-TBCH1H/L) Advance Information 334 Timer Interface Module B (TIMB) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 20. Programmable Interrupt Timer (PIT) 20.1 Contents 20.2 20.3 20.4 20.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 PIT Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 Freescale Semiconductor, Inc... 20.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 20.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 20.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 20.7 PIT During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .338 20.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 20.8.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 339 20.8.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 20.8.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 343 20.2 Introduction This section describes the Programmable Interrupt Timer (PIT) which is a periodic interrupt timer whose counter is clocked internally via software programmable options. Figure 20-1 is a block diagram of the PIT. 20.3 Features Features of the PIT include: * * 68HC908AZ32A -- Rev 0.0 MOTOROLA Programmable Interrupt Timer (PIT) For More Information On This Product, Go to: www.freescale.com Programmable PIT Clock Input Free-Running or Modulo Up-Count Operation Advance Information 335 Freescale Semiconductor, Inc. Programmable Interrupt Timer (PIT) * PIT Counter Stop and Reset Bits 20.4 Functional Description Figure 20-1 shows the structure of the PIT. The central component of the PIT is the 16-bit PIT counter that can operate as a free-running counter or a modulo up-counter. The counter provides the timing reference for the interrupt. The PIT counter modulo registers, PMODH-PMODL, control the modulo value of the counter. Software can read the counter value at any time without affecting the counting sequence. Freescale Semiconductor, Inc... INTERNAL BUS CLOCK CSTOP CRST PRESCALER SELECT PRESCALER PPS2 PPS1 PPS0 16-BIT COUNTER 16-BIT COMPARATOR TIMPMODH:TIMPMODL POF POIE INTERRUPT LOGIC Figure 20-1. PIT Block Diagram Register Name Read: PIT Status and Control Register Write: (PSC) Reset: Read: PIT Counter Register High Write: (PCNTH) Reset: Read: PIT Counter Register Low Write: (PCNTL) Reset: Bit 7 POF 0 0 Bit 15 0 Bit 7 0 6 POIE 0 14 0 6 0 5 PSTOP 1 13 0 5 0 4 0 PRST 0 12 0 4 0 0 11 0 3 0 3 0 2 PPS2 0 10 0 2 0 1 PPS1 0 9 0 1 0 Bit 0 PPS0 0 Bit 8 0 Bit 0 0 =Unimplemented Figure 20-2. PIT I/O Register Summary Advance Information 336 Programmable Interrupt Timer (PIT) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Programmable Interrupt Timer (PIT) PIT Counter Prescaler Register Name Read: PIT Counter Modulo Register High Write: (PMODH) Reset: Read: PIT Counter Modulo Register Low Write: (PMODL) Reset: Bit 7 Bit 15 1 Bit 7 1 6 14 1 6 1 5 13 1 5 1 4 12 1 4 1 3 11 1 3 1 2 10 1 2 1 1 9 1 1 1 Bit 0 Bit 8 1 Bit 0 1 =Unimplemented Freescale Semiconductor, Inc... Figure 20-2. PIT I/O Register Summary Table 20-1. PIT I/O Register Address Summary Register Address PSC $004B PCNTH $004C PCNTL $004D PMODH $004E PMODL $004F 20.5 PIT Counter Prescaler The clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PPS[2:0], in the status and control register select the PIT clock source. The value in the PIT counter modulo registers and the selected prescaler output determines the frequency of the periodic interrupt. The PIT overflow flag (POF) is set when the PIT counter value rolls over to $0000 after matching the value in the PIT counter modulo registers. The PIT interrupt enable bit, POIE, enables PIT overflow CPU interrupt requests. POF and POIE are in the PIT status and control register. 20.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 68HC908AZ32A -- Rev 0.0 MOTOROLA Programmable Interrupt Timer (PIT) For More Information On This Product, Go to: www.freescale.com Advance Information 337 Freescale Semiconductor, Inc. Programmable Interrupt Timer (PIT) 20.6.1 Wait Mode The PIT remains active after the execution of a WAIT instruction. In wait mode the PIT registers are not accessible by the CPU. Any enabled CPU interrupt request from the PIT can bring the MCU out of wait mode. If PIT functions are not required during wait mode, reduce power consumption by stopping the PIT before executing the WAIT instruction. Freescale Semiconductor, Inc... 20.6.2 Stop Mode The PIT is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the PIT counter. PIT operation resumes when the MCU exits stop mode after an external interrupt. 20.7 PIT During Break Interrupts A break interrupt stops the PIT counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state (see SIM Break Flag Control Register on page 134). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. Advance Information 338 Programmable Interrupt Timer (PIT) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Programmable Interrupt Timer (PIT) I/O Registers 20.8 I/O Registers The following I/O registers control and monitor operation of the PIT: * * * PIT status and control register (PSC) PIT counter registers (PCNTH-PCNTL) PIT counter modulo registers (PMODH-PMODL) 20.8.1 TIM Status and Control Register The PIT status and control register: * * * * * Address: Freescale Semiconductor, Inc... Enables PIT interrupt Flags PIT overflows Stops the PIT counter Resets the PIT counter Prescales the PIT counter clock $004B Bit 7 6 POIE 5 PSTOP PRST 0 1 0 0 0 0 0 4 0 3 0 PPS2 PPS1 PPS0 2 1 Bit 0 Read: Write: Reset: POF 0 0 = Unimplemented Figure 20-3. PIT Status and Control Register (PSC) POF -- PIT Overflow Flag Bit This read/write flag is set when the PIT counter resets to $0000 after reaching the modulo value programmed in the PIT counter modulo registers. Clear POF by reading the PIT status and control register when POF is set and then writing a logic 0 to POF. If another PIT overflow occurs before the clearing sequence is complete, then 68HC908AZ32A -- Rev 0.0 MOTOROLA Programmable Interrupt Timer (PIT) For More Information On This Product, Go to: www.freescale.com Advance Information 339 Freescale Semiconductor, Inc. Programmable Interrupt Timer (PIT) writing logic 0 to POF has no effect. Therefore, a POF interrupt request cannot be lost due to inadvertent clearing of POF. Reset clears the POF bit. Writing a logic 1 to POF has no effect. 1 = PIT counter has reached modulo value 0 = PIT counter has not reached modulo value POIE -- PIT Overflow Interrupt Enable Bit This read/write bit enables PIT overflow interrupts when the POF bit becomes set. Reset clears the POIE bit. 1 = PIT overflow interrupts enabled 0 = PIT overflow interrupts disabled PSTOP -- PIT Stop Bit This read/write bit stops the PIT counter. Counting resumes when PSTOP is cleared. Reset sets the PSTOP bit, stopping the PIT counter until software clears the PSTOP bit. 1 = PIT counter stopped 0 = PIT counter active Freescale Semiconductor, Inc... NOTE: Do not set the PSTOP bit before entering wait mode if the PIT is required to exit wait mode. PRST -- PIT Reset Bit Setting this write-only bit resets the PIT counter and the PIT prescaler. Setting PRST has no effect on any other registers. Counting resumes from $0000. PRST is cleared automatically after the PIT counter is reset and always reads as logic zero. Reset clears the PRST bit. 1 = Prescaler and PIT counter cleared 0 = No effect NOTE: Setting the PSTOP and PRST bits simultaneously stops the PIT counter at a value of $0000. Advance Information 340 Programmable Interrupt Timer (PIT) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Programmable Interrupt Timer (PIT) I/O Registers PPS[2:0] -- Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the PIT counter as Table 20-2 shows. Reset clears the PPS[2:0] bits. Table 20-2. Prescaler Selection PPS[2:0] 000 001 010 011 100 101 110 111 PIT Clock Source Internal Bus Clock /1 Internal Bus Clock / 2 Internal Bus Clock / 4 Internal Bus Clock / 8 Internal Bus Clock / 16 Internal Bus Clock / 32 Internal Bus Clock / 64 Internal Bus Clock / 64 Freescale Semiconductor, Inc... 20.8.2 TIM Counter Registers The two read-only PIT counter registers contain the high and low bytes of the value in the PIT counter. Reading the high byte (PCNTH) latches the contents of the low byte (PCNTL) into a buffer. Subsequent reads of PCNTH do not affect the latched PCNTL value until PCNTL is read. Reset clears the PIT counter registers. Setting the PIT reset bit (PRST) also clears the PIT counter registers. NOTE: If you read PCNTH during a break interrupt, be sure to unlatch PCNTL by reading PCNTL before exiting the break interrupt. Otherwise, PCNTL retains the value latched during the break 68HC908AZ32A -- Rev 0.0 MOTOROLA Programmable Interrupt Timer (PIT) For More Information On This Product, Go to: www.freescale.com Advance Information 341 Freescale Semiconductor, Inc. Programmable Interrupt Timer (PIT) . Address: $004C Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8 Freescale Semiconductor, Inc... Address: $004D Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8 = Unimplemented Figure 20-4. PIT Counter Registers (PCNTH-PCNTL) Advance Information 342 Programmable Interrupt Timer (PIT) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Programmable Interrupt Timer (PIT) I/O Registers 20.8.3 TIM Counter Modulo Registers The read/write PIT modulo registers contain the modulo value for the PIT counter. When the PIT counter reaches the modulo value the overflow flag (POF) becomes set and the PIT counter resumes counting from $0000 at the next clock. Writing to the high byte (PMODH) inhibits the POF bit and overflow interrupts until the low byte (PMODL) is written. Reset sets the PIT counter modulo registers. Address: $004E:$004F Bit 7 Read: Bit 15 Write: Reset: 1 1 1 1 1 1 1 1 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Address: $004E:$004F Bit 7 Read: Bit 7 Write: Reset: 1 1 1 1 1 1 1 1 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 Figure 20-5. PIT Counter Modulo Registers (PMODH-PMODL) NOTE: Reset the PIT counter before writing to the PIT counter modulo registers. 68HC908AZ32A -- Rev 0.0 MOTOROLA Programmable Interrupt Timer (PIT) For More Information On This Product, Go to: www.freescale.com Advance Information 343 Freescale Semiconductor, Inc. Programmable Interrupt Timer (PIT) Freescale Semiconductor, Inc... Advance Information 344 Programmable Interrupt Timer (PIT) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 21. Analog-To-Digital Converter (ADC-15) 21.1 Contents 21.2 21.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Freescale Semiconductor, Inc... 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 21.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 21.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 21.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 21.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 21.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 21.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 21.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 21.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 21.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 21.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 21.7.1 ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 21.7.2 ADC Analog Ground Pin (VSSA)/ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 21.7.3 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 350 21.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 21.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 351 21.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 21.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 354 68HC908AZ32A -- Rev 0.0 MOTOROLA Analog-To-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Advance Information 345 Freescale Semiconductor, Inc. Analog-To-Digital Converter (ADC-15) 21.2 Introduction This section describes the analog-to-digital converter (ADC-15). The ADC is an 8-bit analog-to-digital converter. 21.3 Features Features of the ADC module include: * * * * * * 15 Channels with Multiplexed Input Linear Successive Approximation 8-Bit Resolution Single or Continuous Conversion Conversion Complete Flag or Conversion Complete Interrupt Selectable ADC Clock Freescale Semiconductor, Inc... 21.4 Functional Description Fifteen ADC channels are available for sampling external sources at pins PTD6/ATD14/TCLK-PTD0/ATD8 and PTB7-PTB0. An analog multiplexer allows the single ADC converter to select one of 15 ADC channels as ADC voltage in (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. When the conversion is completed, ADC places the result in the ADC data register and sets a flag or generates an interrupt. See Figure 21-1. Advance Information 346 Analog-To-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Analog-To-Digital Converter (ADC-15) Functional Description INTERNAL DATA BUS READ DDRB/DDRB WRITE DDRB/DDRD RESET WRITE PTB/PTD DDRBx/DDRDx PTBx/PTDx DISABLE PTBx/PTDx ADC CHANNEL x READ PTB/PTD Freescale Semiconductor, Inc... DISABLE ADC DATA REGISTER INTERRUPT LOGIC CONVERSION COMPLETE ADC ADC VOLTAGE IN ADCVIN CHANNEL SELECT ADCH[4:0] AIEN COCO ADC CLOCK CGMXCLK BUS CLOCK CLOCK GENERATOR ADIV[2:0] ADICLK Figure 21-1. ADC Block Diagram 21.4.1 ADC Port I/O Pins PTD6/ATD14/TCLK-PTD0/ATD8 and PTB7-PTB0 are general-purpose I/O pins that share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the 68HC908AZ32A -- Rev 0.0 MOTOROLA Analog-To-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Advance Information 347 Freescale Semiconductor, Inc. Analog-To-Digital Converter (ADC-15) ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read. NOTE: Do not use ADC channels ATD14 or ATD12 when using the PTD6/ATD14/TCLK or PTD4/ATD12 pins as the clock inputs for the 16bit Timers. 21.4.2 Voltage Conversion When the input voltage to the ADC equals VREFH (see ADC Characteristics on page 448), the ADC converts the signal to $FF (full scale). If the input voltage equals VSSA, the ADC converts it to $00. Input voltages between VREFH and VSSA are a straight-line linear conversion. Conversion accuracy of all other input voltages is not guaranteed. Avoid current injection on unused ADC inputs to prevent potential conversion error. Freescale Semiconductor, Inc... NOTE: Input voltage should not exceed the analog supply voltages. 21.4.3 Conversion Time Conversion starts after a write to the ADSCR (ADC status control register, $0038), and requires between 16 and 17 ADC clock cycles to complete. Conversion time in terms of the number of bus cycles is a function of ADICLK select, CGMXCLK frequency, bus frequency, and ADIV prescaler bits. For example, with a CGMXCLK frequency of 4 MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz, one conversion will take between 16 and 17 s and there will be between 128 bus cycles between each conversion. Sample rate is approximately 60 kHz. Refer to ADC Characteristics on page 448. 16 to 17 ADC Clock Cycles Conversion Time = ADC Clock Frequency Number of Bus Cycles = Conversion Time x Bus Frequency Advance Information 348 Analog-To-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Analog-To-Digital Converter (ADC-15) Interrupts 21.4.4 Continuous Conversion In the continuous conversion mode, the ADC data register will be filled with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit (ADC status control register, $0038) is cleared. The COCO bit is set after the first conversion and will stay set for the next several conversions until the next write of the ADC status and control register or the next read of the ADC data register. Freescale Semiconductor, Inc... 21.4.5 Accuracy and Precision The conversion process is monotonic and has no missing codes. See ADC Characteristics on page 448 for accuracy information. 21.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit (ADC status control register, $0038) is at logic 0. If the COCO bit is set, an interrupt is generated. The COCO bit is not used as a conversion complete flag when interrupts are enabled. 21.6 Low-Power Modes The following subsections describe the low-power modes. 21.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits in the ADC status and control register before executing the WAIT instruction. 68HC908AZ32A -- Rev 0.0 MOTOROLA Analog-To-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Advance Information 349 Freescale Semiconductor, Inc. Analog-To-Digital Converter (ADC-15) 21.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode. 21.7 I/O Signals The ADC module has 15 channels that are shared with I/O ports B and D. Refer to ADC Characteristics on page 448 for voltages referenced below. Freescale Semiconductor, Inc... 21.7.1 ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH) The ADC analog portion uses VDDAREF as its power pin. Connect the VDDA/VDDAREF pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAREF for good results. VREFH is the high reference voltage for all analog-to-digital conversions. NOTE: Route VDDAREF carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. VDDAREF must be present for operation of the ADC. 21.7.2 ADC Analog Ground Pin (VSSA)/ADC Voltage Reference Low Pin (VREFL) The ADC analog portion uses VSSA as its ground pin. Connect the VSSA pin to the same voltage potential as VSS. VREFL is the lower reference supply for the ADC. 21.7.3 ADC Voltage In (ADCVIN) ADCVIN is the input voltage signal from one of the 15 ADC channels to the ADC module. Advance Information 350 Analog-To-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Analog-To-Digital Converter (ADC-15) I/O Registers 21.8 I/O Registers These I/O registers control and monitor ADC operation: * * * ADC status and control register (ADSCR) ADC data register (ADR) ADC clock register (ADICLK) 21.8.1 ADC Status and Control Register The following paragraphs describe the function of the ADC status and control register. Address: $0038 Bit 7 Read: Write: Reset: COCO AIEN R 0 R 0 = Reserved 0 1 1 1 1 1 ADCO CH4 CH3 CH2 CH1 CH0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 21-2. ADC Status and Control Register (ADSCR) COCO -- Conversions Complete Bit When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the ADC status and control register is written or whenever the ADC data register is read. If the AIEN bit is a logic 1, the COCO is a read/write bit which selects the CPU to service the ADC interrupt request. Reset clears this bit. 1 = conversion completed (AIEN = 0) 0 = conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1) 68HC908AZ32A -- Rev 0.0 MOTOROLA Analog-To-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Advance Information 351 Freescale Semiconductor, Inc. Analog-To-Digital Converter (ADC-15) AIEN -- ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO -- ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH[4:0] -- ADC Channel Select Bits ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field which is used to select one of 15 ADC channels. Channel selection is detailed in the following table. Care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. See Table 21-1. The ADC subsystem is turned off when the channel select bits are all set to one. This feature allows for reduced power consumption for the MCU when the ADC is not used. Reset sets these bits. Freescale Semiconductor, Inc... NOTE: Recovery from the disabled state requires one conversion cycle to stabilize. Table 21-1. Mux Channel Select ADCH4 0 0 0 0 0 0 ADCH3 0 0 0 0 0 0 ADCH2 0 0 0 0 1 1 ADCH1 0 0 1 1 0 0 ADCH0 0 1 0 1 0 1 Input Select PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 Advance Information 352 Analog-To-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Analog-To-Digital Converter (ADC-15) I/O Registers Table 21-1. Mux Channel Select ADCH4 0 0 0 0 0 0 0 0 0 ADCH3 0 0 1 1 1 1 1 1 1 ADCH2 1 1 0 0 0 0 1 1 1 ADCH1 1 1 0 0 1 1 0 0 1 ADCH0 0 1 0 1 0 1 0 1 0 Input Select PTB6 PTB7 PTD0/ATD8/ATD8 PTD1/ATD9/ATD9 PTD2/ATD10/ATD10 PTD3/ATD11/ATD11 PTD4/ATD12/ATD12 PTD5/ATD13/ATD13 PTD6/ATD14/TCLK/A TD14 Unused (see Note 1) Unused (see Note 1) 1 0 1 0 1 Reserved Unused (see Note 1) VREFH (see Note 2) VSSA/VREFL (see Note 2) [ADC power off] Freescale Semiconductor, Inc... Range 01111 ($0F) to 11010 ($1A) 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 NOTES: 1. If any unused channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in production test and for user applications. 68HC908AZ32A -- Rev 0.0 MOTOROLA Analog-To-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Advance Information 353 Freescale Semiconductor, Inc. Analog-To-Digital Converter (ADC-15) 21.8.2 ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes. Address: $0039 Bit 7 Read: Write: Reset: R = Reserved AD7 R 6 AD6 R 5 AD5 R 4 AD4 R 3 AD3 R 2 AD2 R 1 AD1 R Bit 0 AD0 R Freescale Semiconductor, Inc... Indeterminate after Reset Figure 21-3. ADC Data Register (ADR) 21.8.3 ADC Input Clock Register This register selects the clock frequency for the ADC. Address: $003A Bit 7 Read: ADIV2 Write: Reset: 0 6 ADIV1 0 = Reserved 5 ADIV0 0 4 ADICLK 3 0 R 2 0 R 0 1 0 R 0 Bit 0 0 R 0 0 0 R Figure 21-4. ADC Input Clock Register (ADICLK) ADIV2-ADIV0 -- ADC Clock Prescaler Bits ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 212 shows the available clock configurations. The ADC clock should be set to approximately 1 MHz. Advance Information 354 Analog-To-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Analog-To-Digital Converter (ADC-15) I/O Registers Table 21-2. ADC Clock Divide Ratio ADIV2 0 0 0 0 1 ADIV1 0 0 1 1 X ADIV0 0 1 0 1 X ADC Clock Rate ADC Input Clock /1 ADC Input Clock / 2 ADC Input Clock / 4 ADC Input Clock / 8 ADC Input Clock / 16 Freescale Semiconductor, Inc... X = don't care ADICLK -- ADC Input Clock Register Bit ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be guaranteed. See ADC Characteristics on page 448. 1 = Internal bus clock 0 = External clock (CGMXCLK) fXCLK or Bus Frequency 1 MHz = ADIV[2:0] NOTE: During the conversion process, changing the ADC clock will result in an incorrect conversion. 68HC908AZ32A -- Rev 0.0 MOTOROLA Analog-To-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com Advance Information 355 Freescale Semiconductor, Inc. Analog-To-Digital Converter (ADC-15) Freescale Semiconductor, Inc... Advance Information 356 Analog-To-Digital Converter (ADC-15) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 22. Keyboard Module (KBD) 22.1 Contents 22.2 22.3 22.4 22.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Freescale Semiconductor, Inc... 22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 22.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 22.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 22.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .362 22.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 22.8.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 363 22.8.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 364 22.2 Introduction The keyboard interrupt module (KBD) provides five independently maskable external interrupt pins. This module is only available on 64-pin package options. 22.3 Features KBD features include: * * 68HC908AZ32A -- Rev 0.0 MOTOROLA Keyboard Module (KBD) For More Information On This Product, Go to: www.freescale.com Five Keyboard Interrupt Pins with Separate Keyboard Interrupt Enable Bits and One Keyboard Interrupt Mask Hysteresis Buffers Advance Information 357 Freescale Semiconductor, Inc. Keyboard Module (KBD) * * * Programmable Edge-Only or Edge- and Level- Interrupt Sensitivity Automatic Interrupt Acknowledge Exit from Low-Power Modes 22.4 Functional Description Writing to the KBIE4-KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port G or port H pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. * If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. Freescale Semiconductor, Inc... * Advance Information 358 Keyboard Module (KBD) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc... INTERNAL BUS MOTOROLA VDD RESET . D SYNCHRONIZER CK KEYBOARD INTERRUPT REQUEST Q . KB0IE . KEYBOARD INTERRUPT FF IMASKK CLR KEYF ACKK VECTOR FETCH DECODER MODEK KB4IE KBD0 68HC908AZ32A -- Rev 0.0 TO PULLUP ENABLE KBD4 TO PULLUP ENABLE Figure 22-1. Keyboard Module Block Diagram Bit 7 0 0 0 0 0 0 0 0 0 0 0 KBIE4 0 6 0 5 0 4 0 3 KEYF 0 KBIE3 0 1 IMASKK 0 KBIE2 0 KBIE1 0 Bit 0 MODEK 0 KBIE0 0 2 0 ACKK 0 Register Name Freescale Semiconductor, Inc. Keyboard Module (KBD) For More Information On This Product, Go to: www.freescale.com = Unimplemented Read: Keyboard Status and Control RegWrite: ister (KBSCR) Reset: Read: Keyboard Interrupt Enable RegisWrite: ter (KBIER) Reset: Figure 22-2. I/O Register Summary Table 22-1. I/O Register Address Summary Register Address KBSCR $001A KBIER $001B Keyboard Module (KBD) Functional Description Advance Information 359 Freescale Semiconductor, Inc. Keyboard Module (KBD) If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFDE and $FFDF. Return of all enabled keyboard interrupt pins to logic 1. As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. Freescale Semiconductor, Inc... * The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling edgesensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. Advance Information 360 Keyboard Module (KBD) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Keyboard Module (KBD) Keyboard Initialization NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. 22.5 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore, a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRG bits in data direction register G. 2. Configure the keyboard pins as outputs by setting the appropriate DDRH bits in data direction register H. 3. Write logic 1s to the appropriate port G and port H data register bits. 4. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information Keyboard Module (KBD) For More Information On This Product, Go to: www.freescale.com 361 Freescale Semiconductor, Inc. Keyboard Module (KBD) 22.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes. 22.6.1 Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. Freescale Semiconductor, Inc... 22.6.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. 22.7 Keyboard Module During Break Interrupts The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See Section 11. Break Module. To allow software to clear the KEYF bit during a break interrupt, write a logic 1 to the BCFE bit. If KEYF is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the KEYF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0, writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. See Keyboard Status and Control Register on page 363. Advance Information 362 Keyboard Module (KBD) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Keyboard Module (KBD) I/O Registers 22.8 I/O Registers The following registers control and monitor operation of the keyboard module: * * Keyboard status and control register (KBSCR) Keyboard interrupt enable register (KBIER) 22.8.1 Keyboard Status and Control Register The keyboard status and control register: * * * * Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity Freescale Semiconductor, Inc... Address: $001A Bit 7 Read: Write: Reset: 0 0 0 0 0 0 6 0 5 0 4 0 3 KEYF 2 0 IMASKK ACKK 0 0 0 MODEK 1 Bit 0 = Unimplemented Figure 22-3. Keyboard Status and Control Register (KBSCR) Bits 7-4 -- Not used These read-only bits always read as logic 0s. KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending 68HC908AZ32A -- Rev 0.0 MOTOROLA Keyboard Module (KBD) For More Information On This Product, Go to: www.freescale.com Advance Information 363 Freescale Semiconductor, Inc. Keyboard Module (KBD) ACKK -- Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK -- Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK -- Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only Freescale Semiconductor, Inc... 22.8.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port G and each port H pin to operate as a keyboard interrupt pin. Address: $001B Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 4 3 2 1 Bit 0 = Unimplemented Figure 22-4. Keyboard Interrupt Enable Register (KBIER) KBIE4-KBIE0 -- Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = PDx pin enabled as keyboard interrupt pin 0 = PDx pin not enabled as keyboard interrupt pin Advance Information 364 Keyboard Module (KBD) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 23. I/O Ports 23.1 Contents 23.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Freescale Semiconductor, Inc... 23.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 23.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 23.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . 367 23.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 23.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 23.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . 370 23.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 23.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 23.5.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . 373 23.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 376 23.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 23.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 23.7.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . . 380 23.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 23.8.1 Port F Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 23.8.2 Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . . . 383 23.9 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385 23.9.1 Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 23.9.2 Data Direction Register G . . . . . . . . . . . . . . . . . . . . . . . . . 386 23.10 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 23.10.1 Port H Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 23.10.2 Data Direction Register H. . . . . . . . . . . . . . . . . . . . . . . . . . 389 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 365 Freescale Semiconductor, Inc. I/O Ports 23.2 Introduction On the 68HC908AZ32A, fifty bidirectional input/output (I/O) form seven parallel ports. All I/O pins are programmable as inputs or outputs. NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. Figure 23-1. I/O Port Register Summary Freescale Semiconductor, Inc... Addr. $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F Register Name Port A Data Register (PTA) Port B Data Register (PTB) Port C Data Register (PTC) Port D Data Register (PTD) Bit 7 PTA7 PTB7 0 PTD7 6 PTA6 PTB6 0 PTD6 5 PTA5 PTB5 PTC5 PTD5 4 PTA4 PTB4 PTC4 PTD4 3 PTA3 PTB3 PTC3 PTD3 2 PTA2 PTB2 PTC2 PTD2 1 PTA1 PTB1 PTC1 PTD1 Bit 0 PTA0 PTB0 PTC0 PTD0 Data Direction Register A (DDRA) DDRA7 Data Direction Register B (DDRB) DDRB7 Data Direction Register C (DDRC) MCLKEN Data Direction Register D (DDRD) DDRD7 Port E Data Register (PTE) Port F Data Register (PTF) Port G Data Register (PTG) Port H Data Register (PTH) PTE7 0 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 PTE6 PTF6 0 0 PTE5 PTF5 0 0 PTE4 PTF4 0 0 PTE3 PTF3 0 0 PTE2 PTF2 PTG2 0 PTE1 PTF1 PTG1 PTH1 PTE0 PTF0 PTG0 PTH0 Data Direction Register E (DDRE) DDRE7 Data Direction Register F (DDRF) Data Direction Register G (DDRG) Data Direction Register H (DDRH) 0 0 0 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 DDRF6 0 0 DDRF5 0 0 DDRF4 0 0 DDRF3 0 0 DDRF2 DDRF1 DDRF0 DDRG2 DDRG1 DDRG0 0 DDRH1 DDRH0 Advance Information 366 I/O Ports For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. I/O Ports Port A 23.3 Port A Port A is an 8-bit general-purpose bidirectional I/O port. 23.3.1 Port A Data Register The port A data register contains a data latch for each of the eight port A pins. Address: $0000 Bit 7 Read: PTA7 Write: Reset: Unaffected by Reset PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 23-2. Port A Data Register (PTA) PTA[7:0] -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. 23.3.2 Data Direction Register A Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer. Address: $0004 Bit 7 Read: DDRA7 Write: Reset: 0 0 0 0 0 0 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 6 5 4 3 2 1 Bit 0 Figure 23-3. Data Direction Register A (DDRA) 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 367 Freescale Semiconductor, Inc. I/O Ports DDRA[7:0] -- Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE: Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 23-4 shows the port A I/O logic. Freescale Semiconductor, Inc... READ DDRA ($0004) WRITE DDRA ($0004) INTERNAL DATA BUS RESET WRITE PTA ($0000) PTAx PTAx DDRAx READ PTA ($0000) Figure 23-4. Port A I/O Circuit When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 23-1 summarizes the operation of the port A pins. Advance Information 368 I/O Ports For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. I/O Ports Port B Table 23-1. Port A Pin Functions DDRA Bit 0 1 PTA Bit X X I/O Pin Mode Input, Hi-Z Output Accesses to DDRA Read/Write DDRA[7:0] DDRA[7:0] Accesses to PTA Read Pin PTA[7:0] Write PTA[7:0](1) PTA[7:0] X = don't care Hi-Z = high impedance 1. Writing affects data register, but does not affect input. Freescale Semiconductor, Inc... 23.4 Port B Port B is an 8-bit special function port that shares all of its pins with the analog-to-digital converter. 23.4.1 Port B Data Register The port B data register contains a data latch for each of the eight port B pins. Address: $0001 Bit 7 Read: PTB7 Write: Reset: Alternate Functions: ATD7 ATD6 ATD5 Unaffected by Reset ATD4 ATD3 ATD2 ATD1 ATD0 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 6 5 4 3 2 1 Bit 0 Figure 23-5. Port B Data Register (PTB) PTB[7:0] -- Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 369 Freescale Semiconductor, Inc. I/O Ports ATD[7:0] -- ADC Channels PTB7-PTB0 are eight of the analog-to-digital converter channels. The ADC channel select bits, CH[4:0], determine whether the PTB7-PTB0 pins are ADC channels or general-purpose I/O pins. If an ADC channel is selected and a read of this corresponding bit in the port B data register occurs, the data will be 0 if the data direction for this bit is programmed as an input. Otherwise, the data will reflect the value in the data latch. (See Section 21. Analog-To-Digital Converter (ADC-15)). Data direction register B (DDRB) does not affect the data direction of port B pins that are being used by the ADC. However, the DDRB bits always determine whether reading port B returns to the states of the latches or logic 0. Freescale Semiconductor, Inc... 23.4.2 Data Direction Register B Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. Address: $0005 Bit 7 Read: DDRB7 Write: Reset: 0 0 0 0 0 0 0 0 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 6 5 4 3 2 1 Bit 0 Figure 23-6. Data Direction Register B (DDRB) DDRB[7:0] -- Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE: Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 23-7 shows the port B I/O logic. Advance Information 370 I/O Ports For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. I/O Ports Port B READ DDRB ($0005) WRITE DDRB ($0005) INTERNAL DATA BUS RESET WRITE PTB ($0001) PTBx PTBx DDRBx READ PTB ($0001) Freescale Semiconductor, Inc... Figure 23-7. Port B I/O Circuit When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 23-2 summarizes the operation of the port B pins. Table 23-2. Port B Pin Functions DDRB Bit 0 1 PTB Bit X X I/O Pin Mode Input, Hi-Z Output Accesses to DDRB Read/Write DDRB[7:0] DDRB[7:0] Accesses to PTB Read Pin PTB[7:0] Write PTB[7:0](1) PTB[7:0] X = don't care Hi-Z = high impedance 1. Writing affects data register, but does not affect input. 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 371 Freescale Semiconductor, Inc. I/O Ports 23.5 Port C Port C is an 6-bit general-purpose bidirectional I/O port. Note that PTC5 is only available on 64-pin package options. 23.5.1 Port C Data Register The port C data register contains a data latch for each of the six port C pins. Address: $0002 Bit 7 Read: Write: Reset: R Alternate Functions: = Reserved MCLK 0 R 6 0 PTC5 R Unaffected by Reset PTC4 PTC3 PTC2 PTC1 PTC0 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 23-8. Port C Data Register (PTC) PTC[5:0] -- Port C Data Bits These read/write bits are software-programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data (5:0). MCLK -- System Clock Bit The system clock is driven out of PTC2 when enabled by MCLKEN bit in PTCDDR7. Advance Information 372 I/O Ports For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. I/O Ports Port C 23.5.2 Data Direction Register C Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer. Address: $0006 Bit 7 Read: MCLKEN Write: Reset: 0 R R 0 = Reserved 0 0 0 0 0 0 6 0 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 23-9. Data Direction Register C (DDRC) MCLKEN -- MCLK Enable Bit This read/write bit enables MCLK to be an output signal on PTC2. If MCLK is enabled, DDRC2 has no effect. Reset clears this bit. 1 = MCLK output enabled 0 = MCLK output disabled DDRC[5:0] -- Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input NOTE: Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 23-10 shows the port C I/O logic. 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 373 Freescale Semiconductor, Inc. I/O Ports READ DDRC ($0006) WRITE DDRC ($0006) INTERNAL DATA BUS RESET WRITE PTC ($0002) PTCx PTCx DDRCx READ PTC ($0002) Freescale Semiconductor, Inc... Figure 23-10. Port C I/O Circuit When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 23-3 summarizes the operation of the port C pins. Table 23-3. Port C Pin Functions Bit Value 0 1 0 1 PTC Bit 2 2 X X I/O Pin Mode Input, Hi-Z Output Input, Hi-Z Output Accesses to DDRC Read/Write DDRC[2] DDRC[2] DDRC[5:0] DDRC[5:0] Accesses to PTC Read Pin 0 Pin PTC[5:0] Write PTC2 -- PTC[5:0](1) PTC[5:0] X = don't care Hi-Z = high impedance 1. Writing affects data register, but does not affect input. Advance Information 374 I/O Ports For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. I/O Ports Port D 23.6 Port D Port D is an 8-bit general-purpose I/O port. Note that PTD7 is only available on 64-pin package options. 23.6.1 Port D Data Register Port D is a 8-bit special function port that shares seven of its pins with the analog to digital converter and two with the timer interface modules. Address: $0003 Bit 7 Read: PTD7 Write: Reset: Alternate Functions: R ATD14/ TACLK ATD13 Unaffected by Reset ATD12/ TBCLK ATD11 ATD10 ATD9 ATD8 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 23-11. Port D Data Register (PTD) PTD[7:0] -- Port D Data Bits PTD[7:0] are read/write, software programmable bits. Data direction of PTD[7:0] pins are under the control of the corresponding bit in data direction register D. ATD[14:8] -- ADC Channel Status Bits PTD6/ATD14/TACLK-PTD0/ATD8 are seven of the 15 analog-todigital converter channels. The ADC channel select bits, CH[4:0], determine whether the PTD6/ATD14/TACLK-PTD0/ATD8 pins are ADC channels or general-purpose I/O pins. If an ADC channel is selected and a read of this corresponding bit in the port B data register occurs, the data will be 0 if the data direction for this bit is programmed as an input. Otherwise, the data will reflect the value in the data latch. (See Section 21. Analog-To-Digital Converter (ADC15)). 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 375 Freescale Semiconductor, Inc. I/O Ports Data direction register D (DDRD) does not affect the data direction of port D pins that are being used by the TIMA or TIMB. However, the DDRD bits always determine whether reading port D returns the states of the latches or logic 0. TACLK/TBCLK -- Timer Clock Input Bit The PTD6/ATD14/TCLK pin is the external clock input for the TIMA. The PTD4/ATD12 pin is the external clock input for the TIMB. The prescaler select bits, PS[2:0], select PTD6/ATD14/TCLK or PTD4/ATD12 as the TIM clock input. (See TIMA Channel Status and Control Registers on page 299 and TIMB Channel Status and Control Registers on page 328). When not selected as the TIM clock, PTD6/ATD14/TCLK and PTD4/ATD12 are available for generalpurpose I/O. While TACLK/TBCLK are selected corresponding DDRD bits have no effect. Freescale Semiconductor, Inc... 23.6.2 Data Direction Register D Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer. Address: $0007 Bit 7 Read: DDRD7 Write: Reset: 0 0 0 0 0 0 0 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 6 5 4 3 2 1 Bit 0 Figure 23-12. Data Direction Register D (DDRD) DDRD[7:0] -- Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input NOTE: Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. 68HC908AZ32A -- Rev 0.0 I/O Ports For More Information On This Product, Go to: www.freescale.com MOTOROLA Advance Information 376 Freescale Semiconductor, Inc. I/O Ports Port D Figure 23-13 shows the port D I/O logic. READ DDRD ($0007) WRITE DDRD ($0007) INTERNAL DATA BUS RESET WRITE PTD ($0003) PTDx PTDx DDRDx Freescale Semiconductor, Inc... READ PTD ($0003) Figure 23-13. Port D I/O Circuit When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 23-4 summarizes the operation of the port D pins. Table 23-4. Port D Pin Functions DDRD Bit 0 1 PTD Bit X X I/O Pin Mode Input, Hi-Z Output Accesses to DDRD Read/Write DDRD[7:0] DDRD[7:0] Accesses to PTD Read Pin PTD[7:0] Write PTD[7:0](1) PTD[7:0] X = don't care Hi-Z = high impedance 1. Writing affects data register, but does not affect input. 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 377 Freescale Semiconductor, Inc. I/O Ports 23.7 Port E Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA), two of its pins with the serial communications interface module (SCI), and four of its pins with the serial peripheral interface module (SPI). 23.7.1 Port E Data Register The port E data register contains a data latch for each of the eight port E pins. Address: $0008 Bit 7 Read: PTE7 Write: Reset: Alternate Function: SPSCK MOSI MISO Unaffected by Reset SS TACH1 TACH0 RxD TxD PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 23-14. Port E Data Register (PTE) PTE[7:0] -- Port E Data Bits PTE[7:0] are read/write, software programmable bits. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. SPSCK -- SPI Serial Clock Bit The PTE7/SPSCK pin is the serial clock input of an SPI slave module and serial clock output of an SPI master module. When the SPE bit is clear, the PTE7/SPSCK pin is available for general-purpose I/O. (See SPI Control Register on page 271). MOSI -- Master Out/Slave In Bit The PTE6/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear, the PTE6/MOSI pin is available for general-purpose I/O. Advance Information 378 I/O Ports For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. I/O Ports Port E MISO -- Master In/Slave Out Bit The PTE5/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit, SPE, is clear, the SPI module is disabled, and the PTE5/MISO pin is available for general-purpose I/O. (See SPI Control Register on page 271). SS -- Slave Select Bit The PTE4/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the SPI master bit, SPMSTR, is set and MODFEN bit is low, the PTE4/SS pin is available for general-purpose I/O. (See SS (Slave Select) on page 269). When the SPI is enabled as a slave, the DDRF0 bit in data direction register E (DDRE) has no effect on the PTE4/SS pin. Freescale Semiconductor, Inc... NOTE: Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SPI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. (See Table 23-5). TACH[1:0] -- Timer Channel I/O Bits The PTE3/TCH1-PTE2/TCH0 pins are the TIM input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTE3/TCH1-PTE2/TCH0 pins are timer channel I/O pins or general-purpose I/O pins. (See TIMA Channel Status and Control Registers on page 299). NOTE: Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the TIM. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. (See Table 23-5). RxD -- SCI Receive Data Input Bit The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. (See SCI Control Register 1 on page 229). 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 379 Freescale Semiconductor, Inc. I/O Ports TxD -- SCI Transmit Data Output The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. (See SCI Control Register 1 on page 229). NOTE: Freescale Semiconductor, Inc... Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. (See Table 23-5). 23.7.2 Data Direction Register E Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer. Address: $000C Bit 7 Read: DDRE7 Write: Reset: 0 0 0 0 0 0 0 0 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 6 5 4 3 2 1 Bit 0 Figure 23-15. Data Direction Register E (DDRE) DDRE[7:0] -- Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input NOTE: Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1. Figure 23-16 shows the port E I/O logic. Advance Information 380 I/O Ports For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. I/O Ports Port E READ DDRE ($000C) WRITE DDRE ($000C) INTERNAL DATA BUS RESET WRITE PTE ($0008) PTEx PTEx DDREx READ PTE ($0008) Freescale Semiconductor, Inc... Figure 23-16. Port E I/O Circuit When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 23-5 summarizes the operation of the port E pins. Table 23-5. Port E Pin Functions DDRE Bit 0 1 PTE Bit X X I/O Pin Mode Input, Hi-Z Output Accesses to DDRE Read/Write DDRE[7:0] DDRE[7:0] Accesses to PTE Read Pin PTE[7:0] Write PTE[7:0](1) PTE[7:0] X = don't care Hi-Z = high impedance 1. Writing affects data register, but does not affect input. 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 381 Freescale Semiconductor, Inc. I/O Ports 23.8 Port F Port F is a 7-bit special function port that shares four of its pins with the timer interface module (TIMA-6) and two of its pins with the timer interface module (TIMB) on the 68HC908AZ32A. Note that PTF4, PTF5 and PTF6 are only available on 64-pin package options. 23.8.1 Port F Data Register The port F data register contains a data latch for each of the seven port F pins. Address: $0009 Bit 7 Read: Write: Reset: Alternate Function: R = Reserved TBCH1 0 PTF6 R Unaffected by Reset TBCH0 TACH5 TACH4 TACH3 TACH2 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 23-17. Port F Data Register (PTF) PTF[6:0] -- Port F Data Bits These read/write bits are software programmable. Data direction of each port F pin is under the control of the corresponding bit in data direction register F. Reset has no effect on PTF[6:0]. TACH[5:2] -- Timer A Channel I/O Bits The PTF3/TCH5-PTF0/TCH2 pins are the TIM input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTF3/TCH5-PTF0/TCH2 pins are timer channel I/O pins or general-purpose I/O pins. (See TIMA Status and Control Register on page 295). Advance Information 382 I/O Ports For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. I/O Ports Port F TBCH[1:0] -- Timer B Channel I/O Bits The PTF5/TBCH1-PTF4 pins are the TIMB input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTF5/TBCH1-PTF4 pins are timer channel I/O pins or general-purpose I/O pins. (See TIMB Status and Control Register on page 324). NOTE: Freescale Semiconductor, Inc... Data direction register F (DDRF) does not affect the data direction of port F pins that are being used by the TIM. However, the DDRF bits always determine whether reading port F returns the states of the latches or the states of the pins. (See Table 23-6). 23.8.2 Data Direction Register F Data direction register F determines whether each port F pin is an input or an output. Writing a logic 1 to a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the output buffer. Address: $000D Bit 7 Read: Write: Reset: 0 DDRF6 R 0 R 0 = Reserved 0 0 0 0 0 0 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 6 5 4 3 2 1 Bit 0 Figure 23-18. Data Direction Register F (DDRF) DDRF[6:0] -- Data Direction Register F Bits These read/write bits control port F data direction. Reset clears DDRF[6:0], configuring all port F pins as inputs. 1 = Corresponding port F pin configured as output 0 = Corresponding port F pin configured as input NOTE: Avoid glitches on port F pins by writing to the port F data register before changing data direction register F bits from 0 to 1. Figure 23-19 shows the port F I/O logic. 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 383 Freescale Semiconductor, Inc. I/O Ports READ DDRF ($000D) WRITE DDRF ($000D) INTERNAL DATA BUS RESET WRITE PTF ($0009) PTFx PTFx DDRFx READ PTF ($0009) Freescale Semiconductor, Inc... Figure 23-19. Port F I/O Circuit When bit DDRFx is a logic 1, reading address $0009 reads the PTFx data latch. When bit DDRFx is a logic 0, reading address $0009 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 23-6 summarizes the operation of the port F pins. Table 23-6. Port F Pin Functions DDRF Bit 0 1 PTF Bit X X I/O Pin Mode Input, Hi-Z Output Accesses to DDRF Read/Write DDRF[6:0] DDRF[6:0] Accesses to PTF Read Pin PTF[6:0] Write PTF[6:0](1) PTF[6:0] X = don't care Hi-Z = high impedance 1. Writing affects data register, but does not affect input. Advance Information 384 I/O Ports For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. I/O Ports Port G 23.9 Port G Port G is a 3-bit special function port that shares all of its pins with the keyboard interrupt module (KBD). Note that Port G is only available on 64-pin package options. 23.9.1 Port G Data Register The port G data register contains a data latch for each of the three port G pins. Address: $000A Bit 7 Read: Write: Reset: Alternate Function: R = Reserved 0 R 6 0 R 5 0 R 4 0 R 3 0 PTG2 R Unaffected by Reset KBD2 KBD1 KBD0 PTG1 PTG0 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 23-20. Port G Data Register (PTG) PTG[2:0] -- Port G Data Bits These read/write bits are software programmable. Data direction of each port G pin is under the control of the corresponding bit in data direction register G. Reset has no effect on PTG[2:0]. KBD[2:0] -- Keyboard Wakeup pins The keyboard interrupt enable bits, KBIE[2:0], in the keyboard interrupt control register, enable the port G pins as external interrupt pins (See Section 22. Keyboard Module (KBD)). Enabling an external interrupt pin will override the corresponding DDRGx. 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 385 Freescale Semiconductor, Inc. I/O Ports 23.9.2 Data Direction Register G Data direction register G determines whether each port G pin is an input or an output. Writing a logic 1 to a DDRG bit enables the output buffer for the corresponding port G pin; a logic 0 disables the output buffer. Address: $000E Bit 7 Read: Write: Reset: 0 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 DDRG2 R 0 0 0 0 DDRG1 DDRG0 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 23-21. Data Direction Register G (DDRG) DDRG[2:0] -- Data Direction Register G Bits These read/write bits control port G data direction. Reset clears DDRG[2:0], configuring all port G pins as inputs. 1 = Corresponding port G pin configured as output 0 = Corresponding port G pin configured as input NOTE: Avoid glitches on port G pins by writing to the port G data register before changing data direction register G bits from 0 to 1. Figure 23-22 shows the port G I/O logic. READ DDRG ($000E) WRITE DDRG ($000E) INTERNAL DATA BUS RESET WRITE PTG ($000A) PTGx PTGx DDRGx READ PTG ($000A) Figure 23-22. Port G I/O Circuit Advance Information 386 I/O Ports For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. I/O Ports Port G When bit DDRGx is a logic 1, reading address $000A reads the PTGx data latch. When bit DDRGx is a logic 0, reading address $000A reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 23-7 summarizes the operation of the port G pins. Table 23-7. Port G Pin Functions DDRG Bit 0 1 PTG Bit X X I/O Pin Mode Input, Hi-Z Output Accesses to DDRG Read/Write DDRG[2:0] DDRG[2:0] Accesses to PTG Read Pin PTG[2:0] Write PTG[2:0](1) PTG[2:0] Freescale Semiconductor, Inc... X = don't care Hi-Z = high impedance 1. Writing affects data register, but does not affect input. 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 387 Freescale Semiconductor, Inc. I/O Ports 23.10 Port H Port H is a 2-bit special function port that shares all of its pins with the keyboard interrupt module (KBD). Note that Port H is only available on 64-pin package options. 23.10.1 Port H Data Register The port H data register contains a data latch for each of the two port H pins. Address: $000B Bit 7 Read: Write: Reset: Alternate Function: R = Reserved 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 PTH1 R Unaffected by Reset KBD4 KBD3 PTH0 1 Bit 0 Freescale Semiconductor, Inc... Figure 23-23. Port H Data Register (PTH) PTH[1:0] -- Port H Data Bits These read/write bits are software programmable. Data direction of each port H pin is under the control of the corresponding bit in data direction register H. Reset has no effect on PTH[1:0]. KBD[4:3] -- Keyboard Wake-up pins The keyboard interrupt enable bits, KBIE[4:3], in the keyboard interrupt control register, enable the port H pins as external interrupt pins (See Section 22. Keyboard Module (KBD)). Advance Information 388 I/O Ports For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. I/O Ports Port H 23.10.2 Data Direction Register H Data direction register H determines whether each port H pin is an input or an output. Writing a logic 1 to a DDRH bit enables the output buffer for the corresponding port H pin; a logic 0 disables the output buffer. Address: $000F Bit 7 Read: Write: Reset: 0 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 R 0 2 0 DDRH1 R 0 0 0 DDRH0 1 Bit 0 Freescale Semiconductor, Inc... Figure 23-24. Data Direction Register H (DDRH) DDRH[1:0] -- Data Direction Register H Bits These read/write bits control port H data direction. Reset clears DDRG[1:0], configuring all port H pins as inputs. 1 = Corresponding port H pin configured as output 0 = Corresponding port H pin configured as input NOTE: Avoid glitches on port H pins by writing to the port H data register before changing data direction register H bits from 0 to 1. Figure 23-25 shows the port H I/O logic. READ DDRH ($000F) WRITE DDRH ($000F) INTERNAL DATA BUS RESET WRITE PTH ($000B) PTHx PTHx DDRHx READ PTH ($000B) Figure 23-25. Port H I/O Circuit 68HC908AZ32A -- Rev 0.0 MOTOROLA I/O Ports For More Information On This Product, Go to: www.freescale.com Advance Information 389 Freescale Semiconductor, Inc. I/O Ports When bit DDRHx is a logic 1, reading address $000B reads the PTHx data latch. When bit DDRHx is a logic 0, reading address $000B reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 23-8 summarizes the operation of the port H pins. Table 23-8. Port H Pin Functions DDRH Bit 0 1 PTH Bit X X I/O Pin Mode Input, Hi-Z Output Accesses to DDRH Read/Write DDRH[1:0] DDRH[1:0] Accesses to PTH Read Pin PTH[1:0] Write PTH[1:0](1) PTH[1:0] Freescale Semiconductor, Inc... X = don't care Hi-Z = high impedance 1. Writing affects data register, but does not affect input. Advance Information 390 I/O Ports For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 24. MSCAN Controller (MSCAN08) 24.1 Contents 24.2 24.3 24.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 Freescale Semiconductor, Inc... 24.5 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 24.5.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 24.5.2 Receive Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 24.5.3 Transmit Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 24.6 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 24.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 24.7.1 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 24.7.2 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 24.8 Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . . 406 24.9 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406 24.9.1 MSCAN08 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 24.9.2 MSCAN08 Soft Reset Mode. . . . . . . . . . . . . . . . . . . . . . . . 409 24.9.3 MSCAN08 Power Down Mode . . . . . . . . . . . . . . . . . . . . . .409 24.9.4 CPU Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410 24.9.5 Programmable Wakeup Function. . . . . . . . . . . . . . . . . . . . 410 24.10 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 24.11 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 24.12 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 24.13 Programmer's Model of Message Storage . . . . . . . . . . . . . . .416 24.13.1 Message Buffer Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 24.13.2 Identifier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 391 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) 24.13.3 Data Length Register (DLR). . . . . . . . . . . . . . . . . . . . . . . . 419 24.13.4 Data Segment Registers (DSRn) . . . . . . . . . . . . . . . . . . . . 420 24.13.5 Transmit Buffer Priority Registers . . . . . . . . . . . . . . . . . . .421 24.14 Programmer's Model of Control Registers . . . . . . . . . . . . . . . 421 24.14.1 MSCAN08 Module Control Register 0 . . . . . . . . . . . . . . . . 424 24.14.2 MSCAN08 Module Control Register 1 . . . . . . . . . . . . . . . . 426 24.14.3 MSCAN08 Bus Timing Register 0 . . . . . . . . . . . . . . . . . . .427 24.14.4 MSCAN08 Bus Timing Register 1 . . . . . . . . . . . . . . . . . . .428 24.14.5 MSCAN08 Receiver Flag Register (CRFLG) . . . . . . . . . . . 430 24.14.6 MSCAN08 Receiver Interrupt Enable Register . . . . . . . . . 433 24.14.7 MSCAN08 Transmitter Flag Register. . . . . . . . . . . . . . . . . 434 24.14.8 MSCAN08 Transmitter Control Register . . . . . . . . . . . . . . 436 24.14.9 MSCAN08 Identifier Acceptance Control Register. . . . . . . 437 24.14.10 MSCAN08 Receive Error Counter . . . . . . . . . . . . . . . . . . .438 24.14.11 MSCAN08 Transmit Error Counter. . . . . . . . . . . . . . . . . . . 439 24.14.12 MSCAN08 Identifier Acceptance Registers . . . . . . . . . . . .439 24.14.13 MSCAN08 Identifier Mask Registers (CIDMR0-3) . . . . . . . 441 Freescale Semiconductor, Inc... 24.2 Introduction The MSCAN08 is the specific implementation of the Motorola scalable controller area network (MSCAN) concept targeted for the Motorola M68HC08 Microcontroller Family. The module is a communication controller implementing the CAN 2.0 A/B protocol as defined in the BOSCH specification dated September 1991. The CAN protocol was primarily, but not exclusively, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the electromagnetic interference (EMI) environment of a vehicle, cost-effectiveness and required bandwidth. MSCAN08 utilizes an advanced buffer arrangement, resulting in a predictable real-time behavior, and simplifies the application software. Advance Information 392 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Features 24.3 Features Basic features of the MSCAN08 are: * * Modular Architecture Implementation of the CAN Protocol -- Version 2.0A/B - Standard and Extended Data Frames. - 0-8 Bytes Data Length. - Programmable Bit Rate up to 1 Mbps Depending on the Actual Bit Timing and the Clock Jitter of the PLL * * * * Support for Remote Frames Double-Buffered Receive Storage Scheme Triple-Buffered Transmit Storage Scheme with Internal Prioritisation Using a "Local Priority" Concept Flexible Maskable Identifier Filter Supports Alternatively One Full Size Extended Identifier Filter or Two 16-Bit Filters or Four 8-Bit Filters Programmable Wakeup Functionality with Integrated Low-Pass Filter Programmable Loop-Back Mode Supports Self-Test Operation Separate Signalling and Interrupt Capabilities for All CAN Receiver and Transmitter Error States (Warning, Error Passive, Bus Off) Programmable MSCAN08 Clock Source Either CPU Bus Clock or Crystal Oscillator Output Programmable Link to On-Chip Timer Interface Module (TIMB) for Time-Stamping and Network Synchronization Low-Power Sleep Mode Freescale Semiconductor, Inc... * * * * * * 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 393 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) 24.4 External Pins The MSCAN08 uses two external pins, one input (RxCAN) and one output (TxCAN). The TxCAN output pin represents the logic level on the CAN: 0 is for a dominant state, and 1 is for a recessive state. A typical CAN system with MSCAN08 is shown in Figure 24-1. CAN STATION 1 CAN NODE 1 CAN NODE 2 CAN NODE N Freescale Semiconductor, Inc... MCU CAN CONTROLLER (MSCAN08) TXCAN RXCAN TRANSCEIVER CAN_H CAN_L C A N BUS Figure 24-1. The CAN System Each CAN station is connected physically to the CAN bus lines through a transceiver chip. The transceiver is capable of driving the large current needed for the CAN and has current protection against defected CAN or defected stations. Advance Information 394 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Message Storage 24.5 Message Storage MSCAN08 facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 24.5.1 Background Modern application layer software is built under two fundamental assumptions: 1. Any CAN node is able to send out a stream of scheduled messages without releasing the bus between two messages. Such nodes will arbitrate for the bus right after sending the previous message and will only release the bus in case of lost arbitration. 2. The internal message queue within any CAN node is organized as such that the highest priority message will be sent out first if more than one message is ready to be sent. Above behavior cannot be achieved with a single transmit buffer. That buffer must be reloaded right after the previous message has been sent. This loading process lasts a definite amount of time and has to be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message being sent and as such reduces the reactiveness requirements on the CPU. Problems may arise if the sending of a message would be finished just while the CPU re-loads the second buffer. In that case, no buffer would then be ready for transmission and the bus would be released. At least three transmit buffers are required to meet the first of the above requirements under all circumstances. The MSCAN08 has three transmit buffers. Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 395 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) The second requirement calls for some sort of internal prioritisation which the MSCAN08 implements with the "local priority" concept described in Receive Structures on page 396. 24.5.2 Receive Structures The received messages are stored in a 2-stage input first in first out (FIFO). The two message buffers are mapped using a Ping Pong arrangement into a single memory area (see Figure 24-2). While the background receive buffer (RxBG) is exclusively associated to the MSCAN08, the foreground receive buffer (RxFG) is addressable by the CPU08. This scheme simplifies the handler software, because only one address area is applicable for the receive process. Both buffers have a size of 13 bytes to store the CAN control bits, the identifier (standard or extended), and the data content (for details, see Programmer's Model of Message Storage on page 416). The receiver full flag (RXF) in the MSCAN08 receiver flag register (CRFLG) (see MSCAN08 Receiver Flag Register (CRFLG) on page 430), signals the status of the foreground receive buffer. When the buffer contains a correctly received message with matching identifier, this flag is set. On reception, each message is checked to see if it passes the filter (for details see Identifier Acceptance Filter on page 400) and in parallel is written into RxBG. The MSCAN08 copies the content of RxBG into RxFG(1), sets the RXF flag, and generates a receive interrupt to the CPU(2). The user's receive handler has to read the received message from RxFG and to reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message which can follow immediately after the IFS field of the CAN frame, is received into RxBG. The overwriting of the background buffer is independent of the identifier filter function. When the MSCAN08 module is transmitting, the MSCAN08 receives its own messages into the background receive buffer, RxBG. It does NOT 1. Only if the RXF flag is not set. 2. The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF also. Freescale Semiconductor, Inc... Advance Information 396 68HC908AZ32A -- Rev 0.0 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Message Storage overwrite RxFG, generate a receive interrupt or acknowledge its own messages on the CAN bus. The exception to this rule is in loop-back mode (see MSCAN08 Module Control Register 1 on page 426), where the MSCAN08 treats its own messages exactly like all other incoming messages. The MSCAN08 receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN08 must be prepared to become receiver. An overrun condition occurs when both the foreground and the background receive message buffers are filled with correctly received messages with accepted identifiers and another message is correctly received from the bus with an accepted identifier. The latter message will be discarded and an error interrupt with overrun indication will be generated if enabled. The MSCAN08 is still able to transmit messages with both receive message buffers filled, but all incoming messages are discarded. Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 397 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) MSCAN08 RxBG CPU08 Ibus RxFG RXF Freescale Semiconductor, Inc... Tx0 TXE PRIO Tx1 TXE PRIO Tx2 TXE PRIO Figure 24-2. User Model for Message Buffer Organization Advance Information 398 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Message Storage 24.5.3 Transmit Structures The MSCAN08 has a triple transmit buffer scheme to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. The three buffers are arranged as shown in Figure 24-2. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Programmer's Model of Message Storage on page 416). An additional transmit buffer priority register (TBPR) contains an 8-bit "local priority" field (PRIO) (see Transmit Buffer Priority Registers on page 421). To transmit a message, the CPU08 has to identify an available transmit buffer which is indicated by a set transmit buffer empty (TXE) flag in the MSCAN08 transmitter flag register (CTFLG) (see MSCAN08 Transmitter Flag Register on page 434). The CPU08 then stores the identifier, the control bits and the data content into one of the transmit buffers. Finally, the buffer has to be flagged ready for transmission by clearing the TXE flag. The MSCAN08 then will schedule the message for transmission and will signal the successful transmission of the buffer by setting the TXE flag. A transmit interrupt is generated(1) when TXE is set and can be used to drive the application software to re-load the buffer. In case more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN08 uses the local priority setting of the three buffers for prioritisation. For this purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software sets this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being emitted from this node. The lowest binary value of the PRIO field is defined as the highest priority. Freescale Semiconductor, Inc... 1. The transmit interrupt will occur only if not masked. A polling scheme can be applied on TXE also. 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 399 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) The internal scheduling process takes place whenever the MSCAN08 arbitrates for the bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message being set up in one of the three transmit buffers. As messages that are already under transmission cannot be aborted, the user has to request the abort by setting the corresponding abort request flag (ABTRQ) in the transmission control register (CTCR). The MSCAN08 will then grant the request, if possible, by setting the corresponding abort request acknowledge (ABTAK) and the TXE flag in order to release the buffer and by generating a transmit interrupt. The transmit interrupt handler software can tell from the setting of the ABTAK flag whether the message was actually aborted (ABTAK = 1) or sent (ABTAK = 0). Freescale Semiconductor, Inc... 24.6 Identifier Acceptance Filter The Identifier Acceptance Registers (CIDAR0-3) define the acceptance patterns of the standard or extended identifier (ID10-ID0 or ID28-ID0). Any of these bits can be marked `don't care' in the Identifier Mask Registers (CIDMR0-3). A filter hit is indicated to the application on software by a set RXF (Receive Buffer Full Flag, see MSCAN08 Receiver Flag Register (CRFLG) on page 430) and two bits in the Identifier Acceptance Control Register (see MSCAN08 Identifier Acceptance Control Register on page 437). These Identifier Hit Flags (IDHIT1-0) clearly identify the filter section that caused the acceptance. They simplify the application software's task to identify the cause of the receiver interrupt. In case that more than one hit occurs (two or more filters match) the lower hit has priority. A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU interrupt loading. The filter is programmable to operate in four different modes: Advance Information 400 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Identifier Acceptance Filter * Single identifier acceptance filter, each to be applied to a) the full 29 bits of the extended identifier and to the following bits of the CAN frame: RTR, IDE, SRR or b) the 11 bits of the standard identifier plus the RTR and IDE bits of CAN 2.0A/B messages. This mode implements a single filter for a full length CAN 2.0B compliant extended identifier. Figure 24-3 shows how the 32-bit filter bank (CIDAR0-3, CIDMR0-3) produces a filter 0 hit. Two identifier acceptance filters, each to be applied to a) the 14 most significant bits of the extended identifier plus the SRR and the IDE bits of CAN2.0B messages, or b) the 11 bits of the identifier plus the RTR and IDE bits of CAN 2.0A/B messages. Figure 24-4 shows how the 32-bit filter bank (CIDAR0-3, CIDMR03) produces filter 0 and 1 hits. Four identifier acceptance filters, each to be applied to the first eight bits of the identifier. This mode implements four independent filters for the first eight bits of a CAN 2.0A/B compliant standard identifier. Figure 24-5 shows how the 32-bit filter bank (CIDAR0-3, CIDMR0-3) produces filter 0 to 3 hits. Closed filter. No CAN message will be copied into the foreground buffer RxFG, and the RXF flag will never be set. * Freescale Semiconductor, Inc... * * ID28 ID10 IDR0 IDR0 ID21 ID20 ID3 ID2 IDR1 IDR1 ID15 ID14 IDE ID10 IDR2 IDR2 ID7 ID6 ID3 ID10 IDR3 IDR3 RTR ID3 AM7 CIDMR0 AM0 AM7 CIDMR1 AM0 AM7 CIDMR2 AM0 AM7 CIDMR3 AM0 AC7 CIDAR0 AC0 AC7 CIDAR1 AC0 AC7 CIDAR2 AC0 AC7 CIDAR3 AC0 ID Accepted (Filter 0 Hit) Figure 24-3. Single 32-Bit Maskable Identifier Acceptance Filter 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 401 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) ID28 ID10 IDR0 IDR0 ID21 ID20 ID3 ID2 IDR1 IDR1 ID15 ID14 IDE ID10 IDR2 IDR2 ID7 ID6 ID3 ID10 IDR3 IDR3 RTR ID3 AM7 CIDMR0 AM0 AM7 CIDMR1 AM0 AC7 CIDAR0 AC0 AC7 CIDAR1 AC0 ID ACCEPTED (FILTER 0 HIT) Freescale Semiconductor, Inc... AM7 CIDMR2 AM0 AM7 CIDMR3 AM0 AC7 CIDAR2 AC0 AC7 CIDAR3 AC0 ID ACCEPTED (FILTER 1 HIT) Figure 24-4. Dual 16-Bit Maskable Acceptance Filters Advance Information 402 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Identifier Acceptance Filter . ID28 ID10 IDR0 IDR0 ID21 ID20 ID3 ID2 IDR1 IDR1 ID15 ID14 IDE ID10 IDR2 IDR2 ID7 ID6 ID3 ID10 IDR3 IDR3 RTR ID3 AM7 CIDMR0 AM0 Freescale Semiconductor, Inc... AC7 CIDAR0 AC0 ID ACCEPTED (FILTER 0 HIT) AM7 CIDMR1 AM0 AC7 CIDAR1 AC0 ID ACCEPTED (FILTER 1 HIT) AM7 CIDMR2 AM0 AC7 CIDAR2 AC0 ID ACCEPTED (FILTER 2 HIT) AM7 CIDMR3 AM0 AC7 CIDAR3 AC0 ID ACCEPTED (FILTER 3 HIT) Figure 24-5. Quadruple 8-Bit Maskable Acceptance Filters 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 403 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) 24.7 Interrupts The MSCAN08 supports four interrupt vectors mapped onto eleven different interrupt sources, any of which can be individually masked (for details see MSCAN08 Receiver Flag Register (CRFLG) on page 430, to MSCAN08 Transmitter Control Register on page 436). * Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXE flags of the empty message buffers are set. Receive Interrupt: A message has been received successfully and loaded into the foreground receive buffer. This interrupt will be emitted immediately after receiving the EOF symbol. The RXF flag is set. Wakeup Interrupt: An activity on the CAN bus occurred during MSCAN08 internal sleep mode or power-down mode (provided SLPAK = WUPIE = 1). Error Interrupt: An overrun, error, or warning condition occurred. The receiver flag register (CRFLG) will indicate one of the following conditions: - Overrun: An overrun condition as described in Receive Structures on page 396, has occurred. - Receiver Warning: The receive error counter has reached the CPU Warning limit of 96. - Transmitter Warning: The transmit error counter has reached the CPU Warning limit of 96. - Receiver Error Passive: The receive error counter has exceeded the error passive limit of 127 and MSCAN08 has gone to error passive state. - Transmitter Error Passive: The transmit error counter has exceeded the error passive limit of 127 and MSCAN08 has gone to error passive state. - Bus Off: The transmit error counter has exceeded 255 and MSCAN08 has gone to bus off state. Freescale Semiconductor, Inc... * * * Advance Information 404 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Interrupts 24.7.1 Interrupt Acknowledge Interrupts are directly associated with one or more status flags in either the MSCAN08 receiver flag register (CRFLG) or the MSCAN08 transmitter flag register (CTFLG). Interrupts are pending as long as one of the corresponding flags is set. The flags in the above registers must be reset within the interrupt handler in order to handshake the interrupt. The flags are reset through writing a `1' to the corresponding bit position. A flag cannot be cleared if the respective condition still prevails. Freescale Semiconductor, Inc... NOTE: Bit manipulation instructions (BSET) shall not be used to clear interrupt flags. 24.7.2 Interrupt Vectors The MSCAN08 supports four interrupt vectors as shown in Table 24-1. The vector addresses and the relative interrupt priority are dependent on the chip integration and to be defined. Table 24-1. MSCAN08 Interrupt Vector Addresses Function Wakeup Source WUPIF Local Mask WUPIE Global Mask RWRNIF TWRNIF Error Interrupts RERRIF TERRIF BOFFIF OVRIF Receive Transmit RXF TXE0 TXE1 TXE2 RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE TXEIE0 TXEIE1 TXEIE2 I Bit 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 405 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) 24.8 Protocol Violation Protection The MSCAN08 will protect the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: * * The receive and transmit error counters cannot be written or otherwise manipulated. All registers which control the configuration of the MSCAN08 can not be modified while the MSCAN08 is on-line. The SFTRES bit in the MSCAN08 module control register (see MSCAN08 Module Control Register 0 on page 424) serves as a lock to protect the following registers: - MSCAN08 module control register 1 (CMCR1) - MSCAN08 bus timing register 0 and 1 (CBTR0 and CBTR1) - MSCAN08 identifier acceptance control register (CIDAC) - MSCAN08 identifier acceptance registers (CIDAR0-3) - MSCAN08 identifier mask registers (CIDMR0-3) * The TxCAN pin is forced to recessive when the MSCAN08 is in any of the Low Power Modes. Freescale Semiconductor, Inc... 24.9 Low Power Modes In addition to normal mode, the MSCAN08 has three modes with reduced power consumption: Sleep, Soft Reset and Power Down modes. In Sleep and Soft Reset mode, power consumption is reduced by stopping all clocks except those to access the registers. In Power Down mode, all clocks are stopped and no power is consumed. The WAIT and STOP instructions put the MCU in low power consumption stand-by modes. Table 24-2 summarizes the combinations of MSCAN08 and CPU modes. A particular combination of modes is entered for the given settings of the bits SLPAK and SFTRES. For all modes, an MSCAN wake-up interrupt can occur only if SLPAK=WUPIE=1. Advance Information 406 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Low Power Modes Table 24-2. MSCAN08 vs CPU operating modes Table 24-3 MSCAN Mode Power Down Sleep Soft Reset Normal CPU Mode STOP SLPAK = X(1) SFTRES = X SLPAK = 1 SFTRES = 0 SLPAK = 0 SFTRES = 1 SLPAK = 0 SFTRES = 0 WAIT or RUN Freescale Semiconductor, Inc... 1. `X' means don't care. 24.9.1 MSCAN08 Sleep Mode The CPU can request the MSCAN08 to enter the low-power mode by asserting the SLPRQ bit in the module configuration register (see Figure 24-6). The time when the MSCAN08 enters Sleep mode depends on its activity: * * * if it is transmitting, it continues to transmit until there is no more message to be transmitted, and then goes into Sleep mode if it is receiving, it waits for the end of this message and then goes into Sleep mode if it is neither transmitting or receiving, it will immediately go into Sleep mode NOTE: The application software must avoid setting up a transmission (by clearing or more TXE flags) and immediately request Sleep mode (by setting SLPRQ). It then depends on the exact sequence of operations whether MSCAN08 starts transmitting or goes into Sleep mode directly. During Sleep mode, the SLPAK flag is set. The application software should use SLPAK as a handshake indication for the request (SLPRQ) to go into Sleep mode. When in Sleep mode, the MSCAN08 stops its internal clocks. However, clocks to allow register accesses still run. If the 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 407 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) MSCAN08 is in buss-off state, it stops counting the 128*11 consecutive recessive bits due to the stopped clocks. The TxCAN pin stays in recessive state. If RXF=1, the message can be read and RXF can be cleared. Copying of RxGB into RxFG doesn't take place while in Sleep mode. It is possible to access the transmit buffers and to clear the TXE flags. No message abort takes place while in Sleep mode. The MSCAN08 leaves Sleep mode (wake-up) when: * * * bus activity occurs or the MCU clears the SLPRQ bit or the MCU sets the SFTRES bit Freescale Semiconductor, Inc... MSCAN08 Running SLPRQ = 0 SLPAK = 0 MCU or MSCAN08 MCU MSCAN08 Sleeping SLPRQ = 1 SLPAK = 1 Sleep Request SLPRQ = 1 SLPAK = 0 MSCAN08 Figure 24-6. Sleep Request/Acknowledge Cycle NOTE: The MCU cannot clear the SLPRQ bit before the MSCAN08 is in Sleep mode (SLPAK=1). After wake-up, the MSCAN08 waits for 11 consecutive recessive bits to synchronize to the bus. As a consequence, if the MSCAN08 is wokenup by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before Sleep mode was entered. All pending actions are executed upon Advance Information 408 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Low Power Modes wake-up: copying of RxBG into RxFG, message aborts and message transmissions. If the MSCAN08 is still in bus-off state after Sleep mode was left, it continues counting the 128*11 consecutive recessive bits. 24.9.2 MSCAN08 Soft Reset Mode In Soft Reset mode, the MSCAN08 is stopped. Registers can still be accessed. This mode is used to initialize the module configuration, bit timing and the CAN message filter. See MSCAN08 Module Control Register 0 on page 424 for a complete description of the Soft Reset mode. When setting the SFTRES bit, the MSCAN08 immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. Freescale Semiconductor, Inc... NOTE: The user is responsible to take care that the MSCAN08 is not active when Soft Reset mode is entered. The recommended procedure is to bring the MSCAN08 into Sleep mode before the SFTRES bit is set. 24.9.3 MSCAN08 Power Down Mode The MSCAN08 is in Power Down mode when the CPU is in Stop mode. When entering the Power Down mode, the MSCAN08 immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. NOTE: The user is responsible to take care that the MSCAN08 is not active when Power Down mode is entered. The recommended procedure is to bring the MSCAN08 into Sleep mode before the STOP instruction is executed. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN08 drives the TxCAN pin into recessive state. In Power Down mode, no registers can be accessed. MSCAN08 bus activity can wake the MCU from CPU Stop/MSCAN08 power-down mode. However, until the oscillator starts up and 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 409 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) synchronisation is achieved the MSCAN08 will not respond to incoming data. 24.9.4 CPU Wait Mode The MSCAN08 module remains active during CPU wait mode. The MSCAN08 will stay synchronized to the CAN bus and generates transmit, receive, and error interrupts to the CPU, if enabled. Any such interrupt will bring the MCU out of wait mode. Freescale Semiconductor, Inc... 24.9.5 Programmable Wakeup Function The MSCAN08 can be programmed to apply a low-pass filter function to the RxCAN input line while in internal sleep mode (see information on control bit WUPM in MSCAN08 Module Control Register 1 on page 426). This feature can be used to protect the MSCAN08 from wake-up due to short glitches on the CAN bus lines. Such glitches can result from electromagnetic inference within noisy environments. 24.10 Timer Link The MSCAN08 will generate a timer signal whenever a valid frame has been received. Because the CAN specification defines a frame to be valid if no errors occurred before the EOF field has been transmitted successfully, the timer signal will be generated right after the EOF. A pulse of one bit time is generated. As the MSCAN08 receiver engine also receives the frames being sent by itself, a timer signal also will be generated after a successful transmission. The previously described timer signal can be routed into the on-chip timer interface module (TIM).This signal is connected to the timer n channel m input(1) under the control of the timer link enable (TLNKEN) bit in the CMCR0. 1. The timer channel being used for the timer link is integration dependent. Advance Information 410 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Clock System After timer n has been programmed to capture rising edge events, it can be used under software control to generate 16-bit time stamps which can be stored with the received message. 24.11 Clock System Figure 24-7 shows the structure of the MSCAN08 clock generation circuitry and its interaction with the clock generation module (CGM). With this flexible clocking scheme the MSCAN08 is able to handle CAN bus rates ranging from 10 kbps up to 1 Mbps. Freescale Semiconductor, Inc... CGMXCLK OSC /2 CGMOUT (TO SIM) BCS PLL /2 CGM MSCAN08 (2 * BUS FREQ.) /2 MSCANCLK PRESCALER CLKSRC (1 .. 64) Figure 24-7. Clocking Scheme The clock source bit (CLKSRC) in the MSCAN08 module control register (CMCR1) (see MSCAN08 Module Control Register 0 on page 424) defines whether the MSCAN08 is connected to the output of the crystal oscillator or to the PLL output. 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 411 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. NOTE: If the system clock is generated from a PLL, it is recommended to select the crystal clock source rather than the system clock source due to jitter considerations, especially at faster CAN bus rates. A programmable prescaler is used to generate out of the MSCAN08 clock the time quanta (Tq) clock. A time quantum is the atomic unit of time handled by the MSCAN08. Freescale Semiconductor, Inc... fTq = fMSCANCLK Presc value A bit time is subdivided into three segments(1)(see Figure 24-8). * * SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. Time segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta. Time segment 2: This segment represents PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long. * Bit rate= fTq No. of time quanta The synchronization jump width (SJW) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. 1. For further explanation of the underlying concepts please refer to ISO/DIS 11 519-1, Section 10.3. Advance Information 412 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Clock System The above parameters can be set by programming the bus timing registers, CBTR0-CBTR1, see MSCAN08 Bus Timing Register 0 on page 427 and MSCAN08 Bus Timing Register 1 on page 428). NOTE: It is the user's responsibility to make sure that the bit timing settings are in compliance with the CAN standard, Table 24-9 gives an overview on the CAN conforming segment settings and the related parameter values. Freescale Semiconductor, Inc... NRZ SIGNAL SYNC _SEG 1 TIME SEGMENT 1 (PROP_SEG + PHASE_SEG1) 4 ... 16 8... 25 TIME QUANTA = 1 BIT TIME TIME SEG. 2 (PHASE_SEG2) 2 ... 8 SAMPLE POINT (SINGLE OR TRIPLE SAMPLING) Figure 24-8. Segments within the Bit Time 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 413 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Table 24-4. Time segment syntax SYNC_SEG Transmit point System expects transitions to occur on the bus during this period. A node in transmit mode will transfer a new value to the CAN bus at this point. A node in receive mode will sample the bus at this point. If the three samples per bit option is selected then this point marks the position of the third sample. Sample point Freescale Semiconductor, Inc... Time Segment 1 5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16 TSEG1 4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 Time Segment 2 2 3 4 5 6 7 8 TSEG2 1 2 3 4 5 6 7 Synchron. Jump Width 1 .. 2 1 .. 3 1 .. 4 1 .. 4 1 .. 4 1 .. 4 1 .. 4 SJW 0 .. 1 0 .. 2 0 .. 3 0 .. 3 0 .. 3 0 .. 3 0 .. 3 Table 24-5. CAN Standard Compliant Bit Time Segment Settings Advance Information 414 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Memory Map 24.12 Memory Map The MSCAN08 occupies 128 bytes in the CPU08 memory space. The absolute mapping is implementation dependent with the base address being a multiple of 128. $xx00 $xx08 $xx09 $xx0D $xx0E $xx0F $xx10 $xx17 $xx18 $xx3F $xx40 $xx4F $xx50 $xx5F $xx60 $xx6F $xx70 $xx7F CONTROL REGISTERS 9 BYTES RESERVED 5 BYTES ERROR COUNTERS 2 BYTES IDENTIFIER FILTER 8 BYTES RESERVED 40 BYTES RECEIVE BUFFER TRANSMIT BUFFER 0 TRANSMIT BUFFER 1 TRANSMIT BUFFER 2 Freescale Semiconductor, Inc... Figure 24-9. MSCAN08 Memory Map 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 415 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) 24.13 Programmer's Model of Message Storage This section details the organization of the receive and transmit message buffers and the associated control registers. For reasons of programmer interface simplification, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13-byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Addr $05b0 $05b1 $05b2 $05b3 $05b4 $05b5 $05b6 $05b7 $05b8 $05b9 $05bA $05bB $05bC $05bD $05bE $05bF Register Name IDENTIFIER REGISTER 0 IDENTIFIER REGISTER 1 IDENTIFIER REGISTER 2 IDENTIFIER REGISTER 3 DATA SEGMENT REGISTER 0 DATA SEGMENT REGISTER 1 DATA SEGMENT REGISTER 2 DATA SEGMENT REGISTER 3 DATA SEGMENT REGISTER 4 DATA SEGMENT REGISTER 5 DATA SEGMENT REGISTER 6 DATA SEGMENT REGISTER 7 DATA LENGTH REGISTER TRANSMIT BUFFER PRIORITY REGISTER(1) UNUSED UNUSED Freescale Semiconductor, Inc... 1. Not applicable for receive buffers Figure 24-10. Message Buffer Organization 24.13.1 Message Buffer Outline Figure 24-11 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 24-12. All bits of the 13-byte data structure are undefined out of reset. NOTE: The foreground receive buffer can be read anytime but cannot be written. The transmit buffers can be read or written anytime. 68HC908AZ32A -- Rev 0.0 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com MOTOROLA Advance Information 416 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Message Storage 24.13.2 Identifier Registers The identifiers consist of either 11 bits (ID10-ID0) for the standard, or 29 bits (ID28-ID0) for the extended format. ID10/28 is the most significant bit and is transmitted first on the bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. SRR -- Substitute Remote Request This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and will be stored as received on the CAN bus for receive buffers. Addr $05b0 $05b1 $05b2 $05b3 $05b4 $05b5 Register Read: IDR0 Write: Read: IDR1 Write: Read: IDR2 Write: Read: IDR3 Write: Read: DSR0 Write: Read: DSR1 Write: DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 Freescale Semiconductor, Inc... Bit 7 6 5 4 3 2 1 Bit 0 Figure 24-11. Receive/Transmit Message Buffer Extended Identifier (IDRn) (Sheet 1 of 2) 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 417 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Addr $05b6 $05b7 $05b8 $05b9 $05bA $05bB $05bC Register Read: DSR2 Write: Read: DSR3 Write: Read: DSR4 Write: Read: DSR5 Write: Read: DSR6 Write: Read: DSR7 Write: Read: DLR Write: Bit 7 DB7 6 DB6 5 DB5 4 DB4 3 DB3 2 DB2 1 DB1 Bit 0 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Freescale Semiconductor, Inc... DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DLC3 DLC2 DLC1 DLC0 = Unimplemented Figure 24-11. Receive/Transmit Message Buffer Extended Identifier (IDRn) (Sheet 2 of 2) Addr $05b0 Register Read: IDR0 Write: Read: Bit 7 ID10 6 ID9 5 ID8 4 ID7 3 ID6 2 ID5 1 ID4 Bit 0 ID3 $05b1 IDR1 Write: Read: ID2 ID1 ID0 RTR IDE(=0) $05b2 IDR2 Write: Read: $05b3 IDR3 Write: = Unimplemented Figure 24-12. Standard Identifier Mapping Advance Information 418 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Message Storage IDE -- ID Extended This flag indicates whether the extended or standard identifier format is applied in this buffer. In case of a receive buffer, the flag is set as being received and indicates to the CPU how to process the buffer identifier registers. In case of a transmit buffer, the flag indicates to the MSCAN08 what type of identifier to send. 1 = Extended format, 29 bits 0 = Standard format, 11 bits RTR -- Remote Transmission Request This flag reflects the status of the remote transmission request bit in the CAN frame. In case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 1 = Remote frame 0 = Data frame Freescale Semiconductor, Inc... 24.13.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. DLC3-DLC0 -- Data Length Code Bits The data length code contains the number of bytes (data byte count) of the respective message. At transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 24-6 shows the effect of setting the DLC bits. 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 419 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Table 24-6. Data Length Codes Data Length Code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Data Byte Count 0 1 2 3 4 5 6 7 8 Freescale Semiconductor, Inc... 24.13.4 Data Segment Registers (DSRn) The eight data segment registers contain the data to be transmitted or received. The number of bytes to be transmitted or being received is determined by the data length code in the corresponding DLR. Advance Information 420 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Control Registers 24.13.5 Transmit Buffer Priority Registers Address: $05bD Bit 7 6 PRIO6 u 5 PRIO5 u 4 PRIO4 u 3 PRIO3 u 2 PRIO2 u 1 PRIO1 u Bit 0 PRIO0 u Read: PRIO7 Write: Reset: u Freescale Semiconductor, Inc... Figure 24-13. Transmit Buffer Priority Register (TBPR) PRIO7-PRIO0 -- Local Priority This field defines the local priority of the associated message buffer. The local priority is used for the internal prioritisation process of the MSCAN08 and is defined to be highest for the smallest binary number. The MSCAN08 implements the following internal prioritisation mechanism: * * * All transmission buffers with a cleared TXE flag participate in the prioritisation right before the SOF is sent. The transmission buffer with the lowest local priority field wins the prioritisation. In case more than one buffer has the same lowest priority, the message buffer with the lower index number wins. 24.14 Programmer's Model of Control Registers The programmer's model has been laid out for maximum simplicity and efficiency. Figure 24-14 gives an overview on the control register block of the MSCAN08. 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 421 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Addr $0500 Register Read: CMCR0 Write: Read: Bit 7 0 6 0 5 0 4 SYNCH 3 TLNKEN 2 SLPAK 1 SLPRQ Bit 0 SFTRES 0 0 0 0 0 LOOPB WUPM CLKSRC $0501 CMCR1 Write: Read: $0502 CBTR0 Write: Read: SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Freescale Semiconductor, Inc... $0503 CBTR1 Write: Read: SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 $0504 CRFLG Write: Read: WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF $0505 CRIER Write: Read: WUPIE 0 RWRNIE ABTAK2 TWRNIE ABTAK1 RERRIE ABTAK0 TERRIE 0 BOFFIE OVRIE RXFIE $0506 CTFLG Write: Read: 0 ABTRQ2 Write: Read: 0 0 IDAM1 Write: Read: IDAM0 0 ABTRQ1 ABTRQ0 0 TXE2 TXE1 TXE0 $0507 CTCR TXEIE2 0 TXEIE1 IDHIT1 TXEIE0 IDHIT0 $0508 CIDAC $0509 Reserved Write: R R R R R R R R = Unimplemented R = Reserved Figure 24-14. MSCAN08 Control Register Structure Advance Information 422 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Control Registers Addr $050E Register Read: CRXERR Write: Read: Bit 7 RXERR7 6 RXERR6 5 RXERR5 4 RXERR4 3 RXERR3 2 RXERR2 1 RXERR1 Bit 0 RXERR0 $050F CTXERR Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 $0510 CIDAR0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Freescale Semiconductor, Inc... $0511 CIDAR1 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 $0512 CIDAR2 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 $0513 CIDAR3 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 $0514 CIDMR0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 $0515 CIDMR1 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 $0516 CIDMR2 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 $0517 CIDMR3 Write: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Figure 24-14. MSCAN08 Control Register Structure (Continued) 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 423 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) 24.14.1 MSCAN08 Module Control Register 0 Address: $0500 Bit 7 6 0 5 0 4 SYNCH TLNKEN 3 2 SLPAK SLPRQ 0 0 SFTRES 1 1 Bit 0 Read: Write: Reset: 0 Freescale Semiconductor, Inc... 0 0 0 0 0 = Unimplemented Figure 24-15. Module Control Register 0 (CMCR0) SYNCH -- Synchronized Status This bit indicates whether the MSCAN08 is synchronized to the CAN bus and as such can participate in the communication process. 1 = MSCAN08 synchronized to the CAN bus 0 = MSCAN08 not synchronized to the CAN bus TLNKEN -- Timer Enable This flag is used to establish a link between the MSCAN08 and the on-chip timer (see Timer Link on page 410). 1 = The MSCAN08 timer signal output is connected to the timer input. 0 = The port is connected to the timer input. SLPAK -- Sleep Mode Acknowledge This flag indicates whether the MSCAN08 is in module internal sleep mode. It shall be used as a handshake for the sleep mode request (see MSCAN08 Sleep Mode on page 407). If the MSCAN08 detects bus activity while in Sleep mode, it clears the flag. 1 = Sleep - MSCAN08 in internal sleep mode 0 = Wakeup - MSCAN08 is not in Sleep mode Advance Information 424 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Control Registers SLPRQ -- Sleep Request, Go to Internal Sleep Mode This flag requests the MSCAN08 to go into an internal power-saving mode (see MSCAN08 Sleep Mode on page 407). 1 = Sleep -- The MSCAN08 will go into internal sleep mode. 0 = Wakeup -- The MSCAN08 will function normally. SFTRES -- Soft Reset When this bit is set by the CPU, the MSCAN08 immediately enters the soft reset state. Any ongoing transmission or reception is aborted and synchronization to the bus is lost. The following registers enter and stay in their hard reset state: CMCR0, CRFLG, CRIER, CTFLG, and CTCR. The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0-3, and CIDMR0-3 can only be written by the CPU when the MSCAN08 is in soft reset state. The values of the error counters are not affected by soft reset. When this bit is cleared by the CPU, the MSCAN08 tries to synchronize to the CAN bus. If the MSCAN08 is not in bus-off state, it will be synchronized after 11 recessive bits on the bus; if the MSCAN08 is in bus-off state, it continues to wait for 128 occurrences of 11 recessive bits. Clearing SFTRES and writing to other bits in CMCR0 must be in separate instructions. 1 = MSCAN08 in soft reset state 0 = Normal operation Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 425 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) 24.14.2 MSCAN08 Module Control Register 1 Address: $0501 Bit 7 6 0 5 0 4 0 3 0 2 LOOPB 0 1 WUPM 0 Bit 0 CLKSRC 0 Read: Write: Reset: 0 0 0 0 0 0 = Unimplemented Freescale Semiconductor, Inc... Figure 24-16. Module Control Register (CMCR1) LOOPB -- Loop Back Self-Test Mode When this bit is set, the MSCAN08 performs an internal loop back which can be used for self-test operation: the bit stream output of the transmitter is fed back to the receiver internally. The RxCAN input pin is ignored and the TxCAN output goes to the recessive state (logic `1'). The MSCAN08 behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state the MSCAN08 ignores the bit sent during the ACK slot of the CAN frame Acknowledge field to insure proper reception of its own message. Both transmit and receive interrupt are generated. 1 = Activate loop back self-test mode 0 = Normal operation WUPM -- Wakeup Mode This flag defines whether the integrated low-pass filter is applied to protect the MSCAN08 from spurious wakeups (see Programmable Wakeup Function on page 410). 1 = MSCAN08 will wake up the CPU only in cases of a dominant pulse on the bus which has a length of at least twup. 0 = MSCAN08 will wake up the CPU after any recessive to dominant edge on the CAN bus. Advance Information 426 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Control Registers CLKSRC -- Clock Source This flag defines which clock source the MSCAN08 module is driven from (see Clock System on page 411). 1 = The MSCAN08 clock source is CGMOUT (see Figure 24-7). 0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 24-7). NOTE: The CMCR1 register can be written only if the SFTRES bit in the MSCAN08 module control register is set Freescale Semiconductor, Inc... 24.14.3 MSCAN08 Bus Timing Register 0 Address: $0502 Bit 7 Read: Write: Reset: SJW1 0 6 SJW0 0 5 BRP5 0 4 BRP4 0 3 BRP3 0 2 BRP2 0 1 BRP1 0 Bit 0 BRP0 0 Figure 24-17. Bus Timing Register 0 (CBTR0) SJW1 and SJW0 -- Synchronization Jump Width The synchronization jump width (SJW) defines the maximum number of time quanta (Tq) clock cycles by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the bus (see Table 24-7). Table 24-7. Synchronization Jump Width SJW1 0 0 1 1 SJW0 0 1 0 1 Synchronization Jump Width 1 Tq cycle 2 Tq cycle 3 Tq cycle 4 Tq cycle 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 427 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) BRP5-BRP0 -- Baud Rate Prescaler These bits determine the time quanta (Tq) clock, which is used to build up the individual bit timing, according toTable 24-8. Table 24-8. Baud Rate Prescaler BRP5 0 0 0 0 BRP4 0 0 0 0 BRP3 0 0 0 0 BRP2 0 0 0 0 BRP1 0 0 1 1 BRP0 0 1 0 1 Prescaler Value (P) 1 2 3 4 Freescale Semiconductor, Inc... : : 1 : : 1 : : 1 : : 1 : : 1 : : 1 : : 64 NOTE: The CBTR0 register can be written only if the SFTRES bit in the MSCAN08 module control register is set. 24.14.4 MSCAN08 Bus Timing Register 1 Address: $0503 Bit 7 Read: SAMP Write: Reset: 0 0 0 0 0 0 0 0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 6 5 4 3 2 1 Bit 0 Figure 24-18. Bus Timing Register 1 (CBTR1) SAMP -- Sampling This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For higher bit rates, SAMP should be cleared, which means that only one sample will be taken per bit. 1 = Three samples per bit(1) 0 = One sample per bit 1. In this case PHASE_SEG1 must be at least 2 time quanta. Advance Information 428 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Control Registers TSEG22-TSEG10 -- Time Segment Time segments within the bit time fix the number of clock cycles per bit time and the location of the sample point. Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in Table 24-10. Table 24-9. Time Segment Values TSEG13 0 0 0 0 TSEG12 0 0 0 0 TSEG11 0 0 1 1 TSEG10 0 1 0 1 Time Segment 1 1 Tq Cycle(1) 2 Tq Cycles(1) 3Tq Cycles(1) 4 Tq Cycles TSEG22 0 0 TSEG21 0 0 TSEG20 0 1 Time Segment 2 1 Tq Cycle(1) 2 Tq Cycles Freescale Semiconductor, Inc... . . 1 . . 1 . . 1 . . 8Tq Cycles . . 1 . . 1 . . 1 . . 1 . . 16 Tq Cycles 1. This setting is not valid. Please refer to Table 24-5 for valid settings. The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit as shown in Table 24-10). Bit time= Pres value * number of Time Quanta fMSCANCLK NOTE: The CBTR1 register can only be written if the SFTRES bit in the MSCAN08 module control register is set. 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 429 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) 24.14.5 MSCAN08 Receiver Flag Register (CRFLG) All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. A flag can be cleared only when the condition which caused the setting is valid no more. Writing a 0 has no effect on the flag setting. Every flag has an associated interrupt enable flag in the CRIER register. A hard or soft reset will clear the register. Address: $0504 Bit 7 Read: WUPIF Write: Reset: 0 0 0 0 0 0 0 0 RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 24-19. Receiver Flag Register (CRFLG) WUPIF -- Wakeup Interrupt Flag If the MSCAN08 detects bus activity while in Sleep mode, it sets the WUPIF flag. If not masked, a wake-up interrupt is pending while this flag is set. 1 = MSCAN08 has detected activity on the bus and requested wake-up. 0 = No wake-up interrupt has occurred. RWRNIF -- Receiver Warning Interrupt Flag This flag is set when the MSCAN08 goes into warning status due to the receive error counter (REC) exceeding 96 and neither one of the Error Interrupt flags or the Bus-off Interrupt flag is set(1). If not masked, an error interrupt is pending while this flag is set. 1 = MSCAN08 has gone into receiver warning status. 0 = No receiver warning status has been reached. 1. Condition to set the flag: RWRNIF = (96 REC) & RERRIF & TERRIF & BOFFIF Advance Information 430 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Control Registers TWRNIF -- Transmitter Warning Interrupt Flag This flag is set when the MSCAN08 goes into warning status due to the transmit error counter (TEC) exceeding 96 and neither one of the error interrupt flags or the bus-off interrupt flag is set(1). If not masked, an error interrupt is pending while this flag is set. 1 = MSCAN08 has gone into transmitter warning status. 0 = No transmitter warning status has been reached. RERRIF -- Receiver Error Passive Interrupt Flag This flag is set when the MSCAN08 goes into error passive status due to the receive error counter exceeding 127 and the bus-off interrupt flag is not set(2). If not masked, an Error interrupt is pending while this flag is set. 1 = MSCAN08 has gone into receiver error passive status. 0 = No receiver error passive status has been reached. TERRIF -- Transmitter Error Passive Interrupt Flag This flag is set when the MSCAN08 goes into error passive status due to the Transmit Error counter exceeding 127 and the Bus-off interrupt flag is not set(3). If not masked, an Error interrupt is pending while this flag is set. 1 = MSCAN08 went into transmit error passive status. 0 = No transmit error passive status has been reached. BOFFIF -- Bus-Off Interrupt Flag This flag is set when the MSCAN08 goes into bus-off status, due to the transmit error counter exceeding 255. It cannot be cleared before the MSCAN08 has monitored 128 times 11 consecutive `recessive' bits on the bus. If not masked, an Error interrupt is pending while this flag is set. 1 = MSCAN08has gone into bus-off status. 0 = No bus-off status has bee reached. Freescale Semiconductor, Inc... 1. Condition to set the flag: TWRNIF = (96 TEC) & RERRIF & TERRIF & BOFFIF 2. Condition to set the flag: RERRIF = (127 REC 255) & BOFFIF 3. Condition to set the flag: TERRIF = (128 TEC 255) & BOFFIF 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 431 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) OVRIF -- Overrun Interrupt Flag This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 1 = A data overrun has been detected since last clearing the flag. 0 = No data overrun has occurred. RXF -- Receive Buffer Full The RXF flag is set by the MSCAN08 when a new message is available in the foreground receive buffer. This flag indicates whether the buffer is loaded with a correctly received message. After the CPU has read that message from the receive buffer the RXF flag must be cleared to release the buffer. A set RXF flag prohibits the exchange of the background receive buffer into the foreground buffer. If not masked, a receive interrupt is pending while this flag is set. 1 = The receive buffer is full. A new message is available. 0 = The receive buffer is released (not full). Freescale Semiconductor, Inc... NOTE: NOTE: To ensure data integrity, no registers of the receive buffer shall be read while the RXF flag is cleared. The CRFLG register is held in the reset state when the SFTRES bit in CMCR0 is set. Advance Information 432 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Control Registers 24.14.6 MSCAN08 Receiver Interrupt Enable Register Address: $0505 Bit 7 6 RWRNIE 0 5 TWRNIE 0 4 RERRIE 0 3 TERRIE 0 2 BOFFIE 0 1 OVRIE 0 Bit 0 RXFIE 0 Read: WUPIE Write: Reset: 0 Freescale Semiconductor, Inc... Figure 24-20. Receiver Interrupt Enable Register (CRIER) WUPIE -- Wakeup Interrupt Enable 1 = A wakeup event will result in a wakeup interrupt. 0 = No interrupt will be generated from this event. RWRNIE -- Receiver Warning Interrupt Enable 1 = A receiver warning status event will result in an error interrupt. 0 = No interrupt is generated from this event. TWRNIE -- Transmitter Warning Interrupt Enable 1 = A transmitter warning status event will result in an error interrupt. 0 = No interrupt is generated from this event. RERRIE -- Receiver Error Passive Interrupt Enable 1 = A receiver error passive status event will result in an error interrupt. 0 = No interrupt is generated from this event. TERRIE -- Transmitter Error Passive Interrupt Enable 1 = A transmitter error passive status event will result in an error interrupt. 0 = No interrupt is generated from this event. BOFFIE -- Bus-Off Interrupt Enable 1 = A bus-off event will result in an error interrupt. 0 = No interrupt is generated from this event. 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 433 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) OVRIE -- Overrun Interrupt Enable 1 = An overrun event will result in an error interrupt. 0 = No interrupt is generated from this event. RXFIE -- Receiver Full Interrupt Enable 1 = A receive buffer full (successful message reception) event will result in a receive interrupt. 0 = No interrupt will be generated from this event. NOTE: Freescale Semiconductor, Inc... The CRIER register is held in the reset state when the SFTRES bit in CMCR0 is set. 24.14.7 MSCAN08 Transmitter Flag Register The Abort Acknowledge flags are read only. The Transmitter Buffer Empty flags are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag setting. The Transmitter Buffer Empty flags each have an associated interrupt enable bit in the CTCR register. A hard or soft reset will resets the register. Address: $0506 Bit 7 Read: Write: Reset: 0 0 0 0 0 1 1 1 0 5 6 ABTAK2 5 ABTAK1 4 ABTAK0 3 0 TXE2 TXE1 TXE0 2 1 Bit 0 = Unimplemented Figure 24-21. Transmitter Flag Register (CTFLG) Advance Information 434 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Control Registers ABTAK2-ABTAK0 -- Abort Acknowledge This flag acknowledges that a message has been aborted due to a pending abort request from the CPU. After a particular message buffer has been flagged empty, this flag can be used by the application software to identify whether the message has been aborted successfully or has been sent. The ABTAKx flag is cleared implicitly whenever the corresponding TXE flag is cleared. 1 = The message has been aborted. 0 = The message has not been aborted, thus has been sent out. TXE2-TXE0 -- Transmitter Empty This flag indicates that the associated transmit message buffer is empty, thus not scheduled for transmission. The CPU must handshake (clear) the flag after a message has been set up in the transmit buffer and is due for transmission. The MSCAN08 sets the flag after the message has been sent successfully. The flag is also set by the MSCAN08 when the transmission request was successfully aborted due to a pending abort request (see Transmit Buffer Priority Registers on page 421). If not masked, a receive interrupt is pending while this flag is set. Clearing a TXEx flag also clears the corresponding ABTAKx flag (ABTAK, see above). When a TXEx flag is set, the corresponding ABTRQx bit (ABTRQ, see MSCAN08 Transmitter Control Register on page 436) is cleared. 1 = The associated message buffer is empty (not scheduled). 0 = The associated message buffer is full (loaded with a message due for transmission). Freescale Semiconductor, Inc... NOTE: NOTE: To ensure data integrity, no registers of the transmit buffers should be written to while the associated TXE flag is cleared. The CTFLG register is held in the reset state when the SFTRES bit in CMCR0 is set. 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 435 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) 24.14.8 MSCAN08 Transmitter Control Register Address: $0507 Bit 7 6 ABTRQ2 5 ABTRQ1 0 4 ABTRQ0 0 0 3 0 TXEIE2 0 TXEIE1 0 TXEIE0 0 2 1 Bit 0 Read: Write: Reset: 0 0 0 Freescale Semiconductor, Inc... = Unimplemented Figure 24-22. Transmitter Control Register (CTCR) ABTRQ2-ABTRQ0 -- Abort Request The CPU sets an ABTRQx bit to request that an already scheduled message buffer (TXE = 0) be aborted. The MSCAN08 will grant the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). When a message is aborted the associated TXE and the abort acknowledge flag (ABTAK) (see MSCAN08 Transmitter Flag Register on page 434) will be set and an TXE interrupt is generated if enabled. The CPU cannot reset ABTRQx. ABTRQx is cleared implicitly whenever the associated TXE flag is set. 1 = Abort request pending 0 = No abort request NOTE: The software must not clear one or more of the TXE flags in CTFLG and simultaneously set the respective ABTRQ bit(s). TXEIE2-TXEIE0 -- Transmitter Empty Interrupt Enable 1 = A transmitter empty (transmit buffer available for transmission) event results in a transmitter empty interrupt. 0 = No interrupt is generated from this event. NOTE: The CTCR register is held in the reset state when the SFTRES bit in CMCR0 is set. Advance Information 436 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Control Registers 24.14.9 MSCAN08 Identifier Acceptance Control Register Address: $0508 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 IDAM1 IDAM0 5 4 3 0 2 0 1 IDHIT1 Bit 0 IDHIT0 = Unimplemented Freescale Semiconductor, Inc... Figure 24-23. Identifier Acceptance Control Register (CIDAC) IDAM1-IDAM0-- Identifier Acceptance Mode The CPU sets these flags to define the identifier acceptance filter organization (see Identifier Acceptance Filter on page 400). Table 24-10 summarizes the different settings. In "filter closed" mode no messages will be accepted so that the foreground buffer will never be reloaded. Table 24-10. Identifier Acceptance Mode Settings IDAM1 0 0 1 1 IDAM0 0 1 0 1 Identifier Acceptance Mode Single 32-Bit Acceptance Filter Two 16-Bit Acceptance Filter Four 8-Bit Acceptance Filters Filter Closed IDHIT1-IDHIT0-- Identifier Acceptance Hit Indicator The MSCAN08 sets these flags to indicate an identifier acceptance hit (see Identifier Acceptance Filter on page 400). Table 24-10 summarizes the different settings. 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 437 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Table 24-11. Identifier Acceptance Hit Indication IDHIT1 0 0 1 1 IDHIT0 0 1 0 1 Identifier Acceptance Hit Filter 0 Hit Filter 1 Hit Filter 2 Hit Filter 3 Hit Freescale Semiconductor, Inc... The IDHIT indicators are always related to the message in the foreground buffer. When a message gets copied from the background to the foreground buffer, the indicators are updated as well. NOTE: The CIDAC register can be written only if the SFTRES bit in the CMCR0 is set. 24.14.10 MSCAN08 Receive Error Counter Address: $050E Bit 7 6 RXERR6 5 RXERR5 4 RXERR4 3 RXERR3 2 RXERR2 1 RXERR1 Bit 0 RXERR0 Read: RXERR7 Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 24-24. Receiver Error Counter (CRXERR) This register reflects the status of the MSCAN08 receive error counter. The register is read only. Advance Information 438 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Control Registers 24.14.11 MSCAN08 Transmit Error Counter Address: $050F Bit 7 6 TXERR6 5 TXERR5 4 TXERR4 3 TXERR3 2 TXERR2 1 TXERR1 Bit 0 TXERR0 Read: TXERR7 Write: Reset: 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Unimplemented Figure 24-25. Transmit Error Counter (CTXERR) This register reflects the status of the MSCAN08 transmit error counter. The register is read only. NOTE: Both error counters may only be read when in Sleep or Soft Reset mode. 24.14.12 MSCAN08 Identifier Acceptance Registers On reception each message is written into the background receive buffer. The CPU is only signalled to read the message, however, if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message will be overwritten by the next message (dropped). The acceptance registers of the MSCAN08 are applied on the IDR0 to IDR3 registers of incoming messages in a bit by bit manner. For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers only the first two (CIDMR0/1 and CIDAR0/1) are applied. 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 439 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) CIDAR0 Address: $0510 Bit 7 6 AC6 5 AC5 4 AC4 3 AC3 2 AC2 1 AC1 Bit 0 AC0 Read: AC7 Write: Reset: CIDAR1 Address: $050511 Bit 7 Read: AC7 Write: Reset: CIDAR2 Address: $0512 Bit 7 Read: AC7 Write: Reset: CIDAR3 Address: $0513 Bit 7 Read: AC7 Write: Reset: Unaffected by Reset AC6 AC5 AC4 AC3 AC2 AC1 AC0 6 5 4 3 2 1 Bit 0 Unaffected by Reset AC6 AC5 AC4 AC3 AC2 AC1 AC0 6 5 4 3 2 1 Bit 0 Unaffected by Reset AC6 AC5 AC4 AC3 AC2 AC1 AC0 6 5 4 3 2 1 Bit 0 Unaffected by Reset Freescale Semiconductor, Inc... Figure 24-26. Identifier Acceptance Registers (CIDAR0-CIDAR3) AC7-AC0 -- Acceptance Code Bits AC7-AC0 comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. NOTE: The CIDAR0-3 registers can be written only if the SFTRES bit in CMCR0 is set Advance Information 440 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) Programmer's Model of Control Registers 24.14.13 MSCAN08 Identifier Mask Registers (CIDMR0-3) The identifier mask registers specify which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. For standard identifiers it is required to program the last three bits (AM2AM0) in the mask register CIDMR1 to `don't care'. CIDMRO Address: $0514 Bit 7 Read: Write: Reset: CIDMR1 Address: $0515 Bit 7 Read: Write: Reset: CIDMR2 Address: $0516 Bit 7 Read: Write: Reset: CIDMR3 Address: $0517 Bit 7 Read: Write: Reset: AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0 AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0 AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0 AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0 Freescale Semiconductor, Inc... Unaffected by Reset Unaffected by Reset Unaffected by Reset Unaffected by Reset Figure 24-27. Identifier Mask Registers (CIDMR0-CIDMR3) AM7-AM0 -- Acceptance Mask Bits If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match will be detected. The message will be accepted if all such bits match. If a bit is set, it 68HC908AZ32A -- Rev 0.0 MOTOROLA MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com Advance Information 441 Freescale Semiconductor, Inc. MSCAN Controller (MSCAN08) indicates that the state of the corresponding bit in the identifier acceptance register will not affect whether or not the message is accepted. 1 = Ignore corresponding acceptance code register bit. 0 = Match corresponding acceptance code register and identifier bits. NOTE: The CIDMR0-3 registers can be written only if the SFTRES bit in the CMCR0 is set Freescale Semiconductor, Inc... Advance Information 442 MSCAN Controller (MSCAN08) For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Section 25. Electrical Specification 25.1 Contents 25.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 25.2.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 25.2.2 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . 445 25.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 25.2.4 5.0 Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . 446 25.2.5 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 25.2.6 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 25.2.7 5.0 Vdc 0.5 V Serial Peripheral Interface (SPI) Timing . . 449 25.2.8 CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . 452 25.2.9 CGM Component Information . . . . . . . . . . . . . . . . . . . . . . 452 25.2.10 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . 453 25.2.11 Timer Module Characteristics. . . . . . . . . . . . . . . . . . . . . . . 454 25.2.12 RAM Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . 454 25.2.13 EEPROM Memory Characteristics . . . . . . . . . . . . . . . . . . . 454 25.2.14 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . 455 25.3 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 25.3.1 64-Pin Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . . . . 456 Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Advance Information Electrical Specification For More Information On This Product, Go to: www.freescale.com 443 Freescale Semiconductor, Inc. Electrical Specification 25.2 Electrical Specifications 25.2.1 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: Freescale Semiconductor, Inc... This device is not guaranteed to operate properly at the maximum ratings. Refer to 5.0 Volt DC Electrical Characteristics on page 446 for guaranteed operating conditions. Rating Supply Voltage Input Voltage Maximum Current Per Pin Excluding VDD and VSS Storage Temperature Maximum Current out of VSS Maximum Current into VDD Reset and IRQ Input Voltage NOTE: Voltages are referenced to VSS. Symbol VDD VIN I TSTG IMVSS IMVDD VHI Value -0.3 to +6.0 VSS -0.3 to VDD +0.3 Unit V V mA 25 -55 to +150 100 100 VDD + 4.5 C mA mA V NOTE: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD). Advance Information 444 Electrical Specification For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Electrical Specification Electrical Specifications 25.2.2 Functional Operating Range Rating Operating Temperature Range(1) Operating Voltage Range Symbol TA VDD Value -40 to TA(MAX) 5.0 0.5v Unit C V 1. TA(MAX) = 125C for part suffix MFU/MFN TA(MAX) = 105C for part suffix VFU/VFN TA(MAX) = 85C for part suffix CFU/CFN Freescale Semiconductor, Inc... NOTE: For applications which use the LVI, Motorola guarantee the functionality of the device down to the LVI trip point (VLVI) within the constraints outlined in Low Voltage Inhibit (LVI). 25.2.3 Thermal Characteristics Characteristic Thermal Resistance QFP (64 Pins) I/O Pin Power Dissipation Power Dissipation (see Note 1) Symbol Value 70 User Determined PD = (IDD x VDD) + PI/O = K/(TJ + 273 C) PD x (TA + 273 C) + (PD2 x JA) TA + PD Unit JA PI/O PD K TJ C/W W W Constant (see Note 2) Average Junction Temperature W/C x JA C NOTES: 1. Power dissipation is a function of temperature 2. K is a constant unique to the device. K can be determined from a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA. 68HC908AZ32A -- Rev 0.0 MOTOROLA Electrical Specification For More Information On This Product, Go to: www.freescale.com Advance Information 445 Freescale Semiconductor, Inc. Electrical Specification 25.2.4 5.0 Volt DC Electrical Characteristics Characteristic Output High Voltage (ILOAD = -2.0 mA) All Ports (ILOAD = -5.0 mA) All Ports Total source current Output Low Voltage (ILOAD = 1.6 mA) All Ports (ILOAD = 10.0 mA) All Ports Total sink current Input High Voltage All Ports, IRQs, RESET, OSC1 Input Low Voltage All Ports, IRQs, RESET, OSC1 VDD Supply Current Run (see Note 2) Wait (see Note 3) Stop (see Note 4) LVI enabled, TA=25 C LVI disabled, TA=25 C LVI enabled, -40 C to +125 C LVI disabled, -40 C to +125 C I/O Ports Hi-Z Leakage Current Input Current Capacitance Ports (As Input or Output) Low-Voltage Reset Inhibit (trip) (recover) VOL IOL(TOT) VIH VIL -- -- -- 0.7 x VDD VSS -- -- -- -- -- 0.4 1.5 15 VDD 0.3 x VDD V V mA V V VOH IOH(TOT) VDD -0.8 VDD -1.5 -- -- -- -- -- -- 10 V V mA Symbol Min Typical Max Unit Freescale Semiconductor, Inc... -- -- IDD -- -- -- -- -1 -1 -- -- 3.80 25 14 100 35 35 20 400 50 500 100 1 1 12 8 4.49 mA mA A A A A A A pF V mV mV V/ms V V IL IIN COUT CIN VLVI VPOR VPORRST RPOR VHI VHI POR ReArm Voltage (see Note 5) POR Reset Voltage (see Note 6) POR Rise Time Ramp Rate (see Note 7) High COP Disable Voltage (see Note 8) Monitor mode entry voltage on IRQ (see Note 10) 0 0 0.02 VDD + 3.0 VDD + 3.0 200 800 -- VDD + 4.5 VDD + 4.5 Advance Information 446 Electrical Specification For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Electrical Specification Electrical Specifications Characteristic Symbol Min Typical Max Unit Freescale Semiconductor, Inc... NOTES: 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40 C to +TA(MAX), unless otherwise noted. 2. Run (Operating) IDD measured using external square wave clock source (fBUS = 8.4 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. Typical values at midpoint of voltage range, 25C only. 3. Wait IDD measured using external square wave clock source (fBUS = 8.4 MHz). All inputs 0.2 Vdc from rail. No dc loads. Less than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. Measured with all modules enabled. Typical values at midpoint of voltage range, 25C only. 4. Stop IDD measured with OSC1 = VSS. Typical values at midpoint of voltage range, 25C only. 5. Maximum is highest voltage that POR is guaranteed. 6. Maximum is highest voltage that POR is possible. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. See Section 13. Computer Operating Properly (COP). VHI applied to RST. 9. Although IDD is proportional to bus frequency, a current of several mA is present even at very low frequencies. 10. See Monitor mode description within Section 13. Computer Operating Properly (COP). VHI applied to IRQ or RST 25.2.5 Control Timing Characteristic Bus Operating Frequency (4.5-5.5 V -- VDD Only) RESET Pulse Width Low IRQ Interrupt Pulse Width Low (Edge-Triggered) IRQ Interrupt Pulse Period 16-Bit Timer (see Note 2) Input Capture Pulse Width (see Note 3) Input Capture Period MSCAN Wake-up Filter Pulse Width (see Note 5) Symbol fBUS tRL tILHI tILIL tTH, tTL tTLTL tWUP Min -- 1.5 1.5 Note 4 2 Note 4 2 Max 8.4 -- -- -- -- -- 5 Unit MHz tcyc tcyc tcyc tcyc s NOTES: 1. VDD = 5.0 Vdc 0.5v, VSS = 0 Vdc, TA = -40 C to TA(MAX), unless otherwise noted. 2. The 2-bit timer prescaler is the limiting factor in determining timer resolution. 3. Refer to Table 18-2 . Mode, Edge, and Level Selection, and supporting note. 4. The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt service routine plus TBD tcyc. 5. The minimum pulse width to wake up the MSCAN module is guaranteed by design but not tested. 68HC908AZ32A -- Rev 0.0 MOTOROLA Electrical Specification For More Information On This Product, Go to: www.freescale.com Advance Information 447 Freescale Semiconductor, Inc. Electrical Specification 25.2.6 ADC Characteristics Characteristic Resolution Absolute Accuracy (VREFL = 0 V, VDDA/VDDAREF = VREFH = 5 V 0.5v) Conversion Range (see Note 1) Power-Up Time Input Leakage (see Note 3) Ports B and D Conversion Time Monotonicity Zero Input Reading Full-Scale Reading Sample Time (see Note 2) Input Capacitance ADC Internal Clock Analog Input Voltage 00 FE 5 -- 500 k VREFL Min 8 -1 VREFL 16 -1 Max 8 +1 VREFH 17 1 Unit Bits LSB V Includes Quantization VREFL = VSSA Conversion Time Period Comments s A ADC Clock Cycles Freescale Semiconductor, Inc... 16 17 Includes Sampling Time Inherent within Total Error 01 FF -- 8 1.048 M VREFH Hex Hex ADC Clock Cycles pF Hz V Not Tested Tested Only at 1 MHz VIN = VREFL VIN = VREFH NOTES: 1. VDD = 5.0 Vdc 0.5v, VSS = 0 Vdc, VDDA/VDDAREF = 5.0 Vdc 0.5v, VSSA = 0 Vdc, VREFH = 5.0 Vdc 0.5v 2. Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. 3. The external system error caused by input leakage current is approximately equal to the product of R source and input current. Advance Information 448 Electrical Specification For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Electrical Specification Electrical Specifications 25.2.7 5.0 Vdc 0.5 V Serial Peripheral Interface (SPI) Timing Num Characteristic Operating Frequency (see Note 3) Master Slave 1 2 3 4 Cycle Time Master Slave Enable Lead Time Enable Lag Time Clock (SCK) High Time Master Slave Clock (SCK) Low Time Master Slave Data Setup Time (Inputs) Master Slave Data Hold Time (Inputs) Master Slave Access Time, Slave (see Note 4) CPHA = 0 CPHA = 1 Slave Disable Time (Hold Time to High-Impedance State) Enable Edge Lead Time to Data Valid (see Note 6) Master Slave Data Hold Time (Outputs, after Enable Edge) Master Slave Data Valid Master (Before Capture Edge) Data Hold Time (Outputs) Master (Before Capture Edge) Symbol fBUS(M) fBUS(S) tcyc(M) tcyc(S) tLead tLag tW(SCKH)M tW(SCKH)S tW(SCKL)M tW(SCKL)S tSU(M) tSU(S) tH(M) tH(S) tA(CP0) tA(CP1) tDIS tEV(M) tEV(S) tHO(M) tHO(S) tV(M) tHO(M) Min fBUS/128 dc 2 1 15 15 100 50 100 50 45 5 0 15 0 0 -- -- -- 0 5 90 100 Max fBUS/2 fBUS 128 -- -- -- -- -- -- -- -- -- -- -- 40 20 25 10 40 -- -- -- -- Unit MHz tcyc ns ns ns Freescale Semiconductor, Inc... 5 ns 6 ns 7 ns 8 9 10 ns ns ns 11 12 13 ns ns ns NOTES: 1. All timing is shown with respect to 30% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI pins. 2. Item numbers refer to dimensions in Figure 25-1 and Figure 25-2. 3. fBUS = the currently active bus frequency for the microcontroller. 4. Time to data active from high-impedance state. 5. With 100 pF on all SPI pins 68HC908AZ32A -- Rev 0.0 MOTOROLA Electrical Specification For More Information On This Product, Go to: www.freescale.com Advance Information 449 Freescale Semiconductor, Inc. Electrical Specification SS (INPUT) SS pin of master held high. 1 SCK (CPOL = 0) (OUTPUT) NOTE 5 4 SCK (CPOL = 1) (OUTPUT) NOTE 5 4 6 7 LSB IN 10 BITS 6-1 11 MASTER LSB OUT MISO (INPUT) 10 MOSI (OUTPUT) MSB IN 11 MASTER MSB OUT 12 13 BITS 6-1 Freescale Semiconductor, Inc... NOTE: This first clock edge is generated internally, but is not seen at the SCK pin. a) SPI Master Timing (CPHA = 0) SS (INPUT) SS pin of master held high. 1 SCK (CPOL = 0) (OUTPUT) 5 4 NOTE SCK (CPOL = 1) (OUTPUT) 5 4 6 7 LSB IN 10 BITS 6-1 11 MASTER LSB OUT NOTE MISO (INPUT) 10 MOSI (OUTPUT) MSB IN 11 MASTER MSB OUT 12 13 BITS 6-1 NOTE: This last clock edge is generated internally, but is not seen at the SCK pin. b) SPI Master Timing (CPHA = 1) Figure 25-1. SPI Master Timing Diagram Advance Information 450 Electrical Specification For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Electrical Specification Electrical Specifications SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (INPUT) SLAVE 6 MOSI (OUTPUT) MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN SLAVE LSB OUT 11 5 4 9 NOTE 11 5 4 3 Freescale Semiconductor, Inc... NOTE: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) 5 4 10 NOTE SLAVE 6 MOSI (INPUT) MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN 9 SLAVE LSB OUT 5 4 3 NOTE: Not defined but normally LSB of character previously transmitted b) SPI Slave Timing (CPHA = 1) Figure 25-2. SPI Slave Timing Diagram 68HC908AZ32A -- Rev 0.0 MOTOROLA Electrical Specification For More Information On This Product, Go to: www.freescale.com Advance Information 451 Freescale Semiconductor, Inc. Electrical Specification 25.2.8 CGM Operating Conditions Characteristic Operating Voltage VSSA Crystal Reference Frequency Module Crystal Reference Frequency Range Nom. Multiplier VCO Center-of-Range Frequency VCO Operating Frequency fCGMRCLK fCGMXCLK fNOM fCGMVRS fCGMVCLK VSS-0.3 1 -- -- 4.9152 4.9152 -- 4.9152 4.9152 4.9152 -- -- VSS+0.3 16 -- -- Note 1 32.0 V MHz MHz MHz MHz Same Frequency as fCGMRCLK Symbol VDDA Min VDD-0.3 Typ -- Max VDD+0.3 Unit V Comments Freescale Semiconductor, Inc... 1. fCGMVRS is a nominal value described and calculated as an example in the Section 8. Clock Generator Module (CGM) section for the desired VCO operating frequency, fCGMVCLK. 25.2.9 CGM Component Information Description Crystal Load Capacitance Crystal Fixed Capacitance Crystal Tuning Capacitance Filter Capacitor Multiply Factor Symbol CL C1 C2 Cfact CF Min -- -- -- -- Typ -- 2 x CL 2 x CL 0.0154 CFACT x (VDDA/ fXCLK) Max -- -- -- -- Unit -- -- -- F/s V See External Filter -- -- Capacitor Pin (CGMXFC) Comments Consult Crystal Manufacturer's Data Consult Crystal Manufacturer's Data Consult Crystal Manufacturer's Data Filter Capacitor -- on page 147 CBYP must provide low AC impedance from f = fCGMXCLK/100 to 100 x fCGMVCLK, so series resistance must be considered. Bypass Capacitor CBYP -- 0.1 -- F Advance Information 452 Electrical Specification For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Electrical Specification Electrical Specifications 25.2.10 CGM Acquisition/Lock Time Information Description Manual Mode Time to Stable Symbol tACQ tAL tLOCK DTRK DUNT DLOCK DUNL nACQ Min -- Typ (8 x VDDA) / (fCGMXCLK x KACQ) (4 x VDDA) / (fCGMXCLK x KTRK) tACQ+tAL -- -- -- -- 32 Max -- Unit s Notes If CF Chosen Correctly If CF Chosen Correctly Manual Stable to Lock Time Manual Acquisition Time Tracking Mode Entry Frequency Tolerance Acquisition Mode Entry Frequency Tolerance LOCK Entry Freq. Tolerance LOCK Exit Freq. Tolerance Reference Cycles per Acquisition Mode Measurement Reference Cycles per Tracking Mode Measurement Automatic Mode Time to Stable Automatic Stable to Lock Time Automatic Lock Time PLL Jitter, Deviation of Average Bus Frequency over 2 ms (note 1) K value for automatic mode time to stable K value -- -- 0 -- -- s s % % % % -- Freescale Semiconductor, Inc... 3.6 7.2 0.9 1.8 -- 6.3 0 0.9 -- nTRK -- 128 (8 x VDDA) / (fXCLK x KACQ) (4 x VDDA) / (fXCLK x KTRK) 0.65 -- -- -- If CF Chosen Correctly If CF Chosen Correctly tACQ tAL tLOCK nACQ/fXCLK nTRK/fXCLK -- 0 s -- 25 s ms % (fCRYS) x (.025%) x (N/4) -- -- N = VCO Freq. Mult. Kacq Ktrk -- -- 0.2 0.004 -- -- NOTES: 1. Guaranteed but not tested. 2. VDD = 5.0 Vdc 0.5 V, VSS = 0 Vdc, TA = -40C to TA (MAX), unless otherwise noted. 3. Conditions for typical and maximum values are for Run mode with fCGMXCLK = 8MHz, fBUSDES = 8MHz, N = 4, L = 7, discharged CF = 15 nF, VDD = 5Vdc. 4. Refer to Phase-Locked Loop (PLL) section for guidance on the use of the PLL. 68HC908AZ32A -- Rev 0.0 MOTOROLA Electrical Specification For More Information On This Product, Go to: www.freescale.com Advance Information 453 Freescale Semiconductor, Inc. Electrical Specification 25.2.11 Timer Module Characteristics Characteristic Input Capture Pulse Width Input Clock Pulse Width Symbol tTIH, tTIL tTCH, tTCL Min 125 (1/fOP) + 5 Max -- -- Unit ns ns 25.2.12 RAM Memory Characteristics Characteristic RAM Data Retention Voltage Symbol VRDR Min 0.7 Max -- Unit V Freescale Semiconductor, Inc... 25.2.13 EEPROM Memory Characteristics Characteristic EEPROM Programming Time per Byte EEPROM Erasing Time per Byte EEPROM Erasing Time per Block EEPROM Erasing Time per Bulk EEPROM Programming Voltage Discharge Period Number of Programming Operations to the Same EEPROM Byte Before Erase (1) EEPROM Write/Erase Cycles @ 10 ms Write Time EEPROM Data Retention After 10,000 Write/Erase Cycles EEPROM Programming Maximum Time to `AUTO' Bit Set EEPROM Erasing Maximum Time to `AUTO' Bit Set Symbol tEEPGM tEEBYTE tEEBLOCK tEEBULK tEEFPV -- -- -- -- -- Min 10 10 10 10 100 -- 10,000 10 -- -- Max -- -- -- -- -- 8 -- -- 500 8 Unit ms ms ms ms s -- Cycles Years s ms NOTES: 1. Programming a byte more times than the specified maximum may affect the data integrity of that byte. The byte must be erased before it can be programmed again. Advance Information 454 Electrical Specification For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Electrical Specification Electrical Specifications 25.2.14 FLASH Memory Characteristics Characteristic FLASH Program Bus Clock Frequency FLASH Read Bus Clock Frequency FLASH Page Erase Time FLASH Mass Erase Time FLASH PGM/ERASE to HVEN Set Up Time FLASH High Voltage Hold Time FLASH High Voltage Hold Time (Mass) FLASH Program Hold Time FLASH Program Time FLASH Return to Read Time FLASH Cumulative Program HV Period FLASH Row Erase Endurance(6) FLASH Row Program Endurance(7) FLASH Data Retention Time(8) Symbol -- fREAD(1) tERASE(2) tMERASE(3) tNVS tNVH tNVHL tPGS tPROG tRCV(4) tHV(5) Min 1 32K 1 4 10 5 100 5 30 1 -- 10,000 10,000 10 4 -- -- -- Max -- 8.4M -- -- -- -- -- -- 40 Unit MHz Hz ms ms s s s s s s ms cycles cycles years Freescale Semiconductor, Inc... 1. fREAD is defined as the frequency range for which the FLASH memory can be read. 2. If the page erase time is longer than tERASE(MIN), there is no erase-disturb, but it reduces the endurance of the FLASH memory. 3. If the mass erase time is longer than tMERASE(MIN), there is no erase-disturb, but it reduces the endurance of the FLASH memory. 4. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump by clearing HVEN to logic 0. 5. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tNVS+ tNVH + tPGS + (tPROGX 64) tHV max. 6. The minimum row erase endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase cycles. 7. The minimum row program endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many program cycles. 8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. 68HC908AZ32A -- Rev 0.0 MOTOROLA Electrical Specification For More Information On This Product, Go to: www.freescale.com Advance Information 455 Freescale Semiconductor, Inc. Electrical Specification 25.3 Mechanical Specifications 25.3.1 64-Pin Quad Flat Pack (QFP) L 48 49 33 0.20 M C A - B S D S 0.20 M H A - B S D S 32 B B P - A, B, D Detail "A" F -AL -BB Freescale Semiconductor, Inc... Detail "A" 64 1 -DA 0.20 M C A - B S D S 0.05 A - B S 0.20 M H A - B S D S Detail "C" E M D Section B-B 0.20 M C A - B S D S Base Metal 16 17 J N 0.05 A - B V U T R Q C -CSeating Plane H G M Datum -H- Plane K W X Dim. A B C D E F G H J K L Min. 13.90 13.90 2.15 0.30 2.00 0.30 -- 0.13 0.65 Max. 14.10 14.10 2.45 0.45 2.40 0.40 0.25 0.23 0.95 Notes 1. Datum Plane -H- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 2. Datums A-B and -D to be determined at Datum Plane -H-. 3. Dimensions S and V to be determined at seating plane -C-. 4. Dimensions A and B do not include mould protrusion. Allowable mould protrusion is 0.25mm per side. Dimensions A and B do include mould mismatch and are determined at Datum Plane -H-. 5. Dimension D does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 total in excess of the D dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. 6. Dimensions and tolerancing per ANSI Y 14.5M, 1982. 7. All dimensions in mm. Dim. M N P Q R S T U V W X Min. 5 0.13 0 0.13 16.95 0.13 0 16.95 0.35 Max. 10 0.17 7 0.30 17.45 -- -- 17.45 0.45 0.40 BSC 0.80 BSC 12.00 REF 1.6 REF Advance Information 456 Electrical Specification For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Advance Information -- 68HC908AZ32A Glossary A -- See "accumulator (A)." accumulator (A) -- An 8-bit general-purpose register in the CPU08. The CPU08 uses the accumulator to hold operands and results of arithmetic and logic operations. acquisition mode -- A mode of PLL operation during startup before the PLL locks on a frequency. Also see "tracking mode." address bus -- The set of wires that the CPU or DMA uses to read and write memory locations. addressing mode -- The way that the CPU determines the operand address for an instruction. The M68HC08 CPU has 16 addressing modes. ALU -- See "arithmetic logic unit (ALU)." arithmetic logic unit (ALU) -- The portion of the CPU that contains the logic circuitry to perform arithmetic, logic, and manipulation operations on operands. asynchronous -- Refers to logic circuits and operations that are not synchronized by a common reference signal. baud rate -- The total number of bits transmitted per unit of time. BCD -- See "binary-coded decimal (BCD)." binary -- Relating to the base 2 number system. binary number system -- The base 2 number system, having two digits, 0 and 1. Binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to correspond to the two digital voltage levels. binary-coded decimal (BCD) -- A notation that uses 4-bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number. For example, 234 (decimal) = 0010 0011 0100 (BCD) bit -- A binary digit. A bit has a value of either logic 0 or logic 1. Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Glossary For More Information On This Product, Go to: www.freescale.com Advance Information 457 Freescale Semiconductor, Inc. Glossary branch instruction -- An instruction that causes the CPU to continue processing at a memory location other than the next sequential address. break module -- A module in the M68HC08 Family. The break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint -- A number written into the break address registers of the break module. When a number appears on the internal address bus that is the same as the number in the break address registers, the CPU executes the software interrupt instruction (SWI). break interrupt -- A software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers. bus -- A set of wires that transfers logic signals. bus clock -- The bus clock is derived from the CGMOUT output from the CGM. The bus clock frequency, fop, is equal to the frequency of the oscillator output, CGMXCLK, divided by four. byte -- A set of eight bits. C -- The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and shifts and rotates). CCR -- See "condition code register." central processor unit (CPU) -- The primary functioning unit of any computer system. The CPU controls the execution of instructions. CGM -- See "clock generator module (CGM)." clear -- To change a bit from logic 1 to logic 0; the opposite of set. clock -- A square wave signal used to synchronize events in a computer. clock generator module (CGM) -- A module in the M68HC08 Family. The CGM generates a base clock signal from which the system clocks are derived. The CGM may include a crystal oscillator circuit and or phase-locked loop (PLL) circuit. comparator -- A device that compares the magnitude of two inputs. A digital comparator defines the equality or relative differences between two binary numbers. computer operating properly module (COP) -- A counter module in the M68HC08 Family that resets the MCU if allowed to overflow. Freescale Semiconductor, Inc... Advance Information 458 Glossary For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Glossary condition code register (CCR) -- An 8-bit register in the CPU08 that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. control bit -- One bit of a register manipulated by software to control the operation of the module. control unit -- One of two major units of the CPU. The control unit contains logic functions that synchronize the machine and direct various operations. The control unit decodes instructions and generates the internal control signals that perform the requested operations. The outputs of the control unit drive the execution unit, which contains the arithmetic logic unit (ALU), CPU registers, and bus interface. COP -- See "computer operating properly module (COP)." counter clock -- The input clock to the TIM counter. This clock is the output of the TIM prescaler. CPU -- See "central processor unit (CPU)." CPU08 -- The central processor unit of the M68HC08 Family. CPU clock -- The CPU clock is derived from the CGMOUT output from the CGM. The CPU clock frequency is equal to the frequency of the oscillator output, CGMXCLK, divided by four. CPU cycles -- A CPU cycle is one period of the internal bus clock, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. The length of time required to execute an instruction is measured in CPU clock cycles. CPU registers -- Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map. The CPU always has direct access to the information in these registers. The CPU registers in an M68HC08 are: * * * * * A (8-bit accumulator) H:X (16-bit index register) SP (16-bit stack pointer) PC (16-bit program counter) Freescale Semiconductor, Inc... CCR (condition code register containing the V, H, I, N, Z, and C bits) CSIC -- customer-specified integrated circuit cycle time -- The period of the operating frequency: tCYC = 1/fOP. decimal number system -- Base 10 numbering system that uses the digits zero through nine. 68HC908AZ32A -- Rev 0.0 MOTOROLA Glossary For More Information On This Product, Go to: www.freescale.com Advance Information 459 Freescale Semiconductor, Inc. Glossary direct memory access module (DMA) -- A M68HC08 Family module that can perform data transfers between any two CPU-addressable locations without CPU intervention. For transmitting or receiving blocks of data to or from peripherals, DMA transfers are faster and more code-efficient than CPU interrupts. DMA -- See "direct memory access module (DMA)." DMA service request -- A signal from a peripheral to the DMA module that enables the DMA module to transfer data. duty cycle -- A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is usually represented by a percentage. EEPROM -- Electrically erasable, programmable, read-only memory. A nonvolatile type of memory that can be electrically reprogrammed. EPROM -- Erasable, programmable, read-only memory. A nonvolatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed. exception -- An event such as an interrupt or a reset that stops the sequential execution of the instructions in the main program. external interrupt module (IRQ) -- A module in the M68HC08 Family with both dedicated external interrupt pins and port pins that can be enabled as interrupt pins. fetch -- To copy data from a memory location into the accumulator. firmware -- Instructions and data programmed into nonvolatile memory. free-running counter -- A device that counts from zero to a predetermined number, then rolls over to zero and begins counting again. full-duplex transmission -- Communication on a channel in which data can be sent and received simultaneously. H -- The upper byte of the 16-bit index register (H:X) in the CPU08. H -- The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from the low-order four bits of the accumulator value to the high-order four bits. The half-carry bit is required for binary-coded decimal arithmetic operations. The decimal adjust accumulator (DAA) instruction uses the state of the H and C bits to determine the appropriate correction factor. hexadecimal -- Base 16 numbering system that uses the digits 0 through 9 and the letters A through F. high byte -- The most significant eight bits of a word. Freescale Semiconductor, Inc... Advance Information 460 Glossary For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Glossary illegal address -- An address not within the memory map illegal opcode -- A nonexistent opcode. I -- The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts are disabled. index register (H:X) -- A 16-bit register in the CPU08. The upper byte of H:X is called H. The lower byte is called X. In the indexed addressing modes, the CPU uses the contents of H:X to determine the effective address of the operand. H:X can also serve as a temporary data storage location. input/output (I/O) -- Input/output interfaces between a computer system and the external world. A CPU reads an input to sense the level of an external signal and writes to an output to change the level on an external signal. instructions -- Operations that a CPU can perform. Instructions are expressed by programmers as assembly language mnemonics. A CPU interprets an opcode and its associated operand(s) and instruction. interrupt -- A temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine. interrupt request -- A signal from a peripheral to the CPU intended to cause the CPU to execute a subroutine. I/O -- See "input/output (I/0)." IRQ -- See "external interrupt module (IRQ)." jitter -- Short-term signal instability. latch -- A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency -- The time lag between instruction completion and data movement. least significant bit (LSB) -- The rightmost digit of a binary number. logic 1 -- A voltage level approximately equal to the input power voltage (VDD). logic 0 -- A voltage level approximately equal to the ground voltage (VSS). low byte -- The least significant eight bits of a word. low voltage inhibit module (LVI) -- A module in the M68HC08 Family that monitors power supply voltage. Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Glossary For More Information On This Product, Go to: www.freescale.com Advance Information 461 Freescale Semiconductor, Inc. Glossary LVI -- See "low voltage inhibit module (LVI)." M68HC08 -- A Motorola family of 8-bit MCUs. mark/space -- The logic 1/logic 0 convention used in formatting data in serial communication. mask -- 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used in integrated circuit fabrication to transfer an image onto silicon. mask option -- A optional microcontroller feature that the customer chooses to enable or disable. mask option register (MOR) -- An EPROM location containing bits that enable or disable certain MCU features. MCU -- Microcontroller unit. See "microcontroller." memory location -- Each M68HC08 memory location holds one byte of data and has a unique address. To store information in a memory location, the CPU places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. To read information from a memory location, the CPU places the address of the location on the address bus and asserts the read signal. In response to the read signal, the selected memory location places its data onto the data bus. memory map -- A pictorial representation of all memory locations in a computer system. microcontroller -- Microcontroller unit (MCU). A complete computer system, including a CPU, memory, a clock oscillator, and input/output (I/O) on a single integrated circuit. modulo counter -- A counter that can be programmed to count to any number from zero to its maximum possible modulus. monitor ROM -- A section of ROM that can execute commands from a host computer for testing purposes. MOR -- See "mask option register (MOR)." most significant bit (MSB) -- The leftmost digit of a binary number. multiplexer -- A device that can select one of a number of inputs and pass the logic level of that input on to the output. N -- The negative bit in the condition code register of the CPU08. The CPU sets the negative bit when an arithmetic operation, logical operation, or data manipulation produces a negative result. nibble -- A set of four bits (half of a byte). Freescale Semiconductor, Inc... Advance Information 462 Glossary For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc. Glossary object code -- The output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code. opcode -- A binary code that instructs the CPU to perform an operation. open-drain -- An output that has no pullup transistor. An external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand -- Data on which an operation is performed. Usually a statement consists of an operator and an operand. For example, the operator may be an add instruction, and the operand may be the quantity to be added. oscillator -- A circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference. OTPROM -- One-time programmable read-only memory. A nonvolatile type of memory that cannot be reprogrammed. overflow -- A quantity that is too large to be contained in one byte or one word. page zero -- The first 256 bytes of memory (addresses $0000-$00FF). parity -- An error-checking scheme that counts the number of logic 1s in each byte transmitted. In a system that uses odd parity, every byte is expected to have an odd number of logic 1s. In an even parity system, every byte should have an even number of logic 1s. In the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts the number of logic 1s in each byte. The parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s. PC -- See "program counter (PC)." peripheral -- A circuit not under direct CPU control. phase-locked loop (PLL) -- A oscillator circuit in which the frequency of the oscillator is synchronized to a reference signal. PLL -- See "phase-locked loop (PLL)." pointer -- Pointer register. An index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore points to the operand. polarity -- The two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage levels, VDD and VSS. polling -- Periodically reading a status bit to monitor the condition of a peripheral device. Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Glossary For More Information On This Product, Go to: www.freescale.com Advance Information 463 Freescale Semiconductor, Inc. Glossary port -- A set of wires for communicating with off-chip devices. prescaler -- A circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program -- A set of computer instructions that cause a computer to perform a desired operation or operations. program counter (PC) -- A 16-bit register in the CPU08. The PC register holds the address of the next instruction or operand that the CPU will use. pull -- An instruction that copies into the accumulator the contents of a stack RAM location. The stack RAM address is in the stack pointer. pullup -- A transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply. pulse-width -- The amount of time a signal is on as opposed to being in its off state. pulse-width modulation (PWM) -- Controlled variation (modulation) of the pulse width of a signal with a constant frequency. push -- An instruction that copies the contents of the accumulator to the stack RAM. The stack RAM address is in the stack pointer. PWM period -- The time required for one complete cycle of a PWM waveform. RAM -- Random access memory. All RAM locations can be read or written by the CPU. The contents of a RAM memory location remain valid until the CPU writes a different value or until power is turned off. RC circuit -- A circuit consisting of capacitors and resistors having a defined time constant. read -- To copy the contents of a memory location to the accumulator. register -- A circuit that stores a group of bits. reserved memory location -- A memory location that is used only in special factory test modes. Writing to a reserved location has no effect. Reading a reserved location returns an unpredictable value. reset -- To force a device to a known condition. ROM -- Read-only memory. A type of memory that can be read but cannot be changed (written). The contents of ROM must be specified before manufacturing the MCU. SCI -- See "serial communication interface module (SCI)." serial -- Pertaining to sequential transmission over a single line. Advance Information 464 Glossary For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary serial communications interface module (SCI) -- A module in the M68HC08 Family that supports asynchronous communication. serial peripheral interface module (SPI) -- A module in the M68HC08 Family that supports synchronous communication. set -- To change a bit from logic 0 to logic 1; opposite of clear. shift register -- A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain. signed -- A binary number notation that accommodates both positive and negative numbers. The most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the magnitude of the number. software -- Instructions and data that control the operation of a microcontroller. software interrupt (SWI) -- An instruction that causes an interrupt and its associated vector fetch. SPI -- See "serial peripheral interface module (SPI)." stack -- A portion of RAM reserved for storage of CPU register contents and subroutine return addresses. stack pointer (SP) -- A 16-bit register in the CPU08 containing the address of the next available storage location on the stack. start bit -- A bit that signals the beginning of an asynchronous serial transmission. status bit -- A register bit that indicates the condition of a device. stop bit -- A bit that signals the end of an asynchronous serial transmission. subroutine -- A sequence of instructions to be used more than once in the course of a program. The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the flow of the main program to execute the instructions in the subroutine. When the RTS instruction is executed, the CPU returns to the main program where it left off. synchronous -- Refers to logic circuits and operations that are synchronized by a common reference signal. TIM -- See "timer interface module (TIM)." Freescale Semiconductor, Inc... 68HC908AZ32A -- Rev 0.0 MOTOROLA Glossary For More Information On This Product, Go to: www.freescale.com Advance Information 465 Freescale Semiconductor, Inc. Glossary timer interface module (TIM) -- A module used to relate events in a system to a point in time. timer -- A module used to relate events in a system to a point in time. toggle -- To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode -- Mode of low-jitter PLL operation during which the PLL is locked on a frequency. Also see "acquisition mode." two's complement -- A means of performing binary subtraction using addition techniques. The most significant bit of a two's complement number indicates the sign of the number (1 indicates negative). The two's complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result. unbuffered -- Utilizes only one register for data; new data overwrites current data. unimplemented memory location -- A memory location that is not used. Writing to an unimplemented location has no effect. Reading an unimplemented location returns an unpredictable value. Executing an opcode at an unimplemented location causes an illegal address reset. V --The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow bit. variable -- A value that changes during the course of program execution. VCO -- See "voltage-controlled oscillator." vector -- A memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset. voltage-controlled oscillator (VCO) -- A circuit that produces an oscillating output signal of a frequency that is controlled by a dc voltage applied to a control input. waveform -- A graphical representation in which the amplitude of a wave is plotted against time. wired-OR -- Connection of circuit outputs so that if any output is high, the connection point is high. word -- A set of two bytes (16 bits). write -- The transfer of a byte of data from the CPU to a memory location. X -- The lower byte of the index register (H:X) in the CPU08. Z -- The zero bit in the condition code register of the CPU08. The CPU08 sets the zero bit when an arithmetic operation, logical operation, or data manipulation produces a result of $00. Advance Information 466 Glossary For More Information On This Product, Go to: www.freescale.com 68HC908AZ32A -- Rev 0.0 MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Freescale Semiconductor, Inc... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2002 MC68HC908AZ32A/D For More Information On This Product, Go to: www.freescale.com |
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